42 lines
1.4 KiB
Verilog
42 lines
1.4 KiB
Verilog
module char_mem (
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input [4:0] addr,
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output [7:0] bus,
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input [3:0] A,
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input [3:0] B,
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input [2:0] opCode,
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input [7:0] Y
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);
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parameter LINES = 2;
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parameter CHARS_PER_LINE = 16;
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parameter BITS_PER_CHAR = 8;
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parameter STR_SIZE = LINES * CHARS_PER_LINE * BITS_PER_CHAR;
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// Map the data into strings for display
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wire [127:0] line1 = { "A:", nibble_to_ascii(A), " B:", nibble_to_ascii(B), " " };
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wire [127:0] line2 = { "op:", nibble_to_ascii({1'b0, opCode}), " Y:", byte_to_ascii(Y) };
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// Combine the two lines
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wire [0:STR_SIZE-1] display_data = { line1, line2 };
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// Address selection for the LCD
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assign bus = display_data[{addr[4:0], 3'b000}+:8];
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// Converts a 4-bit nibble to two ASCII characters
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function [15:0] nibble_to_ascii;
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input [3:0] nibble;
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begin
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nibble_to_ascii[15:8] = (nibble[3:0] >= 4'd10) ? (nibble[3:0] - 4'd10 + "A") : (nibble[3:0] + "0");
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nibble_to_ascii[7:0] = " ";
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end
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endfunction
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// Converts an 8-bit byte to two ASCII characters
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function [15:0] byte_to_ascii;
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input [7:0] byte;
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begin
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byte_to_ascii[15:8] = ((byte >> 4) >= 4'd10) ? ((byte >> 4) - 4'd10 + "A") : ((byte >> 4) + "0");
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byte_to_ascii[7:0] = ((byte & 4'hF) >= 4'd10) ? ((byte & 4'hF) - 4'd10 + "A") : ((byte & 4'hF) + "0");
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end
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endfunction
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endmodule
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