verilog/spartanTest/aluboard.v
2025-01-12 07:23:34 +03:00

9 lines
142 B
Verilog

module aluboard (
input [3:0] select,
input [7:0] Y,
input [3:0] A, B,
input [2:0] opCodeA,
output [7:0] sO
);
ALU alu0 ()