53 lines
2.2 KiB
Verilog
53 lines
2.2 KiB
Verilog
module lcd (
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input clk,
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output reg lcd_rs,
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output reg lcd_rw,
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output reg lcd_e,
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output reg [7:4] lcd_d,
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output [4:0] mem_addr,
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input [7:0] mem_bus
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);
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parameter n = 24;
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parameter j = 17; // Initialization is slow, runs at clk/2^(j+2) ~95Hz
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parameter k = 11; // Writing/seeking is fast, clk/2^(k_2) ~6KHz
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parameter noop = 6'b010000; // Allows LCD to drive lcd_d, can be safely written any time
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reg [n:0] count = 0;
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reg [5:0] lcd_state = noop;
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reg init = 1; // Start in initialization on power on
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reg row = 0; // Writing to top or or bottom row
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assign mem_addr = {row, count[k+6:k+3]};
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initial count[j+7:j+2] = 11;
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always @ (posedge clk) begin
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count <= count + 1;
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if (init) begin // initalization
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case (count[j+7:j+2])
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1: lcd_state <= 6'b000010; // function set
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2: lcd_state <= 6'b000010;
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3: lcd_state <= 6'b001000;
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4: lcd_state <= 6'b000000; // display on/off control
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5: lcd_state <= 6'b001100;
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6: lcd_state <= 6'b000000; // display clear
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7: lcd_state <= 6'b000001;
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8: lcd_state <= 6'b000000; // entry mode set
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9: lcd_state <= 6'b000110;
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10: begin init <= ~init; count <= 0; end
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endcase
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// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
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{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[j+1:j+0] & ~lcd_rw,lcd_state};
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end else begin // Continuously update screen from memory
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case (count[k+7:k+2])
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32: lcd_state <= {3'b001,~row,2'b00}; // Move cursor to begining of next line
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33: lcd_state <= 6'b000000;
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34: begin count <= 0; row <= ~row; end // Restart and switch which row is being written
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default: lcd_state <= {2'b10, ~count[k+2] ? mem_bus[7:4] : mem_bus[3:0]}; // Pull characters from bus
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endcase
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// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
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{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[k+1:k+0] & ~lcd_rw,lcd_state};
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end
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end
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endmodule |