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verilog

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k0rrluna
2024-04-13 05:48:55 +03:00
commit ed465dd690
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lab2_prep/impl/gwsynthesis/lab2.log Normal file
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GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
NOTE (EX0101) : Current top module is "tb"
WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
GowinSynthesis finish

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lab2_prep/impl/gwsynthesis/lab2.prj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\cygwin64\home\koray\verilog\lab2\src\lab2.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab2\src\tb.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

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lab2_prep/impl/gwsynthesis/lab2.vg Normal file
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//
//Written by GowinSynthesis
//Tool Version "V1.9.9.02"
//Thu Apr 11 06:15:18 2024
//Source file index table:
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
`timescale 100 ps/100 ps
module tb (
)
;
wire VCC;
wire GND;
VCC VCC_cZ (
.V(VCC)
);
GND GND_cZ (
.G(GND)
);
GSR GSR (
.GSRI(VCC)
);
endmodule /* tb */

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lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\cygwin64\home\koray\verilog\lab2\src\lab2.v<br>
C:\cygwin64\home\koray\verilog\lab2\src\tb.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Apr 11 06:15:18 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>tb</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>0(0 LUT, 0 ALU) / 20736</td>
<td>0%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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lab2_prep/impl/gwsynthesis/lab2_syn_resource.html Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

2
lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Module name="tb"/>

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lab2_prep/impl/lab2_process_config.json Normal file
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{
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CPU" : false,
"CRC_CHECK" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Disable_Insert_Pad" : false,
"ENABLE_CTP" : false,
"ENABLE_MERGE_MODE" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"ERROR_DECTION_AND_CORRECTION" : false,
"ERROR_DECTION_ONLY" : false,
"ERROR_INJECTION" : false,
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
"Enable_DSRM" : false,
"FORMAT" : "binary",
"FREQUENCY_DIVIDER" : "",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"Global_Freq" : "default",
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"MSPI_JUMP" : false,
"MULTIBOOT_ADDRESS_WIDTH" : "24",
"MULTIBOOT_MODE" : "Normal",
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
"MULTIJUMP_ADDRESS_WIDTH" : "24",
"MULTIJUMP_MODE" : "Normal",
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
"Multi_Boot" : true,
"OUTPUT_BASE_NAME" : "lab2",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : false,
"Replicate_Resources" : false,
"Report_Auto-Placed_Io_Information" : false,
"Route_Maxfan" : 23,
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SEU_HANDLER" : false,
"SEU_HANDLER_CHECKSUM" : false,
"SEU_HANDLER_MODE" : "auto",
"SSPI" : false,
"STOP_SEU_HANDLER" : false,
"Show_All_Warnings" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"VCCAUX" : 3.3,
"VCCX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"show_all_warnings" : false,
"turn_off_bg" : false
}

20
lab2_prep/impl/temp/rtl_parser.result Normal file
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[
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"InstLine" : 1,
"InstName" : "tb",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"ModuleLine" : 1,
"ModuleName" : "tb",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"InstLine" : 6,
"InstName" : "uut",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
"ModuleLine" : 1,
"ModuleName" : "lab2"
}
]
}
]

21
lab2_prep/impl/temp/rtl_parser_arg.json Normal file
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{
"Device" : "GW2A-18C",
"Files" : [
{
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
"Type" : "verilog"
},
{
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

12
lab2_prep/lab2.gprj Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/lab2.v" type="file.verilog" enable="1"/>
<File path="src/tb.v" type="file.verilog" enable="1"/>
<File path="src/labwave" type="file.other" enable="1"/>
</FileList>
</Project>

17
lab2_prep/lab2.gprj.user Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="0"/>
<Process ID="Gao" State="0"/>
<Process ID="Rtl_Gao" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd0000000200000000000001700000013dfc0200000001fc000000630000013d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000114fc0100000001fc0000000000000500000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000003880000013d00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
</UserConfig>

77
lab2_prep/src/dmp.vcd Normal file
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$date
Thu Apr 11 06:20:47 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb $end
$var wire 1 ! w1 $end
$var reg 1 " r1 $end
$var reg 1 # r2 $end
$var reg 1 $ r3 $end
$var reg 1 % r4 $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 & AD $end
$var wire 1 ' An $end
$var wire 1 ( AnBC $end
$var wire 1 # B $end
$var wire 1 ) Bn $end
$var wire 1 $ C $end
$var wire 1 * Cn $end
$var wire 1 + CnD $end
$var wire 1 % D $end
$var wire 1 ! F $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0+
1*
1)
0(
1'
0&
0%
0$
0#
0"
1!
$end
#50
1+
1%
#100
0+
0*
0%
1$
#150
1%
#200
0!
1*
0)
0%
0$
1#
#250
1!
1+
1%
#300
0+
1(
0*
0%
1$
#350
1%
#400

126
lab2_prep/src/lab Normal file
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001e2946aad20 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
v000001e29475e7f0_0 .var "r1", 0 0;
v000001e29475e6b0_0 .var "r2", 0 0;
v000001e29475ec50_0 .var "r3", 0 0;
v000001e29475e430_0 .var "r4", 0 0;
v000001e29475ecf0_0 .net "w1", 0 0, L_000001e29475f0f0; 1 drivers
S_000001e294717fc0 .scope module, "uut" "lab2" 2 6, 3 1 0, S_000001e2946aad20;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "F";
L_000001e2947183d0 .functor NOT 1, v000001e29475e7f0_0, C4<0>, C4<0>, C4<0>;
L_000001e2946e2bc0 .functor AND 1, L_000001e2947183d0, v000001e29475e6b0_0, v000001e29475ec50_0, C4<1>;
L_000001e2946e2d20 .functor NOT 1, v000001e29475e6b0_0, C4<0>, C4<0>, C4<0>;
L_000001e29475f390 .functor AND 1, v000001e29475e7f0_0, v000001e29475e430_0, C4<1>, C4<1>;
L_000001e29475f4e0 .functor NOT 1, v000001e29475ec50_0, C4<0>, C4<0>, C4<0>;
L_000001e29475f780 .functor AND 1, L_000001e29475f4e0, v000001e29475e430_0, C4<1>, C4<1>;
L_000001e29475f0f0 .functor OR 1, L_000001e2946e2bc0, L_000001e2946e2d20, L_000001e29475f390, L_000001e29475f780;
v000001e2946e2a40_0 .net "A", 0 0, v000001e29475e7f0_0; 1 drivers
v000001e2946e28d0_0 .net "AD", 0 0, L_000001e29475f390; 1 drivers
v000001e2946a9e10_0 .net "An", 0 0, L_000001e2947183d0; 1 drivers
v000001e2946aaeb0_0 .net "AnBC", 0 0, L_000001e2946e2bc0; 1 drivers
v000001e294718150_0 .net "B", 0 0, v000001e29475e6b0_0; 1 drivers
v000001e2947181f0_0 .net "Bn", 0 0, L_000001e2946e2d20; 1 drivers
v000001e294718290_0 .net "C", 0 0, v000001e29475ec50_0; 1 drivers
v000001e294718330_0 .net "Cn", 0 0, L_000001e29475f4e0; 1 drivers
v000001e294714e50_0 .net "CnD", 0 0, L_000001e29475f780; 1 drivers
v000001e294714ef0_0 .net "D", 0 0, v000001e29475e430_0; 1 drivers
v000001e29475e390_0 .net "F", 0 0, L_000001e29475f0f0; alias, 1 drivers
.scope S_000001e2946aad20;
T_0 ;
%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
%vpi_call 2 18 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001e29475e7f0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e6b0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475ec50_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001e29475e430_0, 0, 1;
%delay 50, 0;
%vpi_call 2 27 "$display", v000001e29475ecf0_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"lab2.v";

43
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_0000016d6fd625e0 .scope module, "lab2" "lab2" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "F";
o0000016d6fd96f98 .functor BUFZ 1, C4<z>; HiZ drive
L_0000016d6fd62f70 .functor NOT 1, o0000016d6fd96f98, C4<0>, C4<0>, C4<0>;
o0000016d6fd97058 .functor BUFZ 1, C4<z>; HiZ drive
o0000016d6fd970b8 .functor BUFZ 1, C4<z>; HiZ drive
L_0000016d6fedb7d0 .functor AND 1, L_0000016d6fd62f70, o0000016d6fd97058, o0000016d6fd970b8, C4<1>;
L_0000016d6fedb840 .functor NOT 1, o0000016d6fd97058, C4<0>, C4<0>, C4<0>;
o0000016d6fd97148 .functor BUFZ 1, C4<z>; HiZ drive
L_0000016d6fedb8b0 .functor AND 1, o0000016d6fd96f98, o0000016d6fd97148, C4<1>, C4<1>;
L_0000016d6fedb920 .functor NOT 1, o0000016d6fd970b8, C4<0>, C4<0>, C4<0>;
L_0000016d6fedb990 .functor AND 1, L_0000016d6fedb920, o0000016d6fd97148, C4<1>, C4<1>;
L_0000016d6fedba00 .functor OR 1, L_0000016d6fedb7d0, L_0000016d6fedb840, L_0000016d6fedb8b0, L_0000016d6fedb990;
v0000016d6fd62b30_0 .net "A", 0 0, o0000016d6fd96f98; 0 drivers
v0000016d6fd62d50_0 .net "AD", 0 0, L_0000016d6fedb8b0; 1 drivers
v0000016d6fd62770_0 .net "An", 0 0, L_0000016d6fd62f70; 1 drivers
v0000016d6fd62810_0 .net "AnBC", 0 0, L_0000016d6fedb7d0; 1 drivers
v0000016d6fd628b0_0 .net "B", 0 0, o0000016d6fd97058; 0 drivers
v0000016d6fededb0_0 .net "Bn", 0 0, L_0000016d6fedb840; 1 drivers
v0000016d6fedee50_0 .net "C", 0 0, o0000016d6fd970b8; 0 drivers
v0000016d6fedeef0_0 .net "Cn", 0 0, L_0000016d6fedb920; 1 drivers
v0000016d6fedb600_0 .net "CnD", 0 0, L_0000016d6fedb990; 1 drivers
v0000016d6fedb730_0 .net "D", 0 0, o0000016d6fd97148; 0 drivers
v0000016d6fd90c30_0 .net "F", 0 0, L_0000016d6fedba00; 1 drivers
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
"lab2.v";

24
lab2_prep/src/lab2.v Normal file
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module lab2(
input A,
input B,
input C,
input D,
output F
);
wire An, Bn, Cn;
wire AnBC, AD, CnD;
not n1 (An, A);
and (AnBC, An, B, C);
not (Bn, B);
and (AD, A, D);
not (Cn, C);
and (CnD, Cn, D);
or (F, AnBC, Bn, AD, CnD);
endmodule

43
lab2_prep/src/labwave Normal file
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001e0df4625e0 .scope module, "f_lab2" "f_lab2" 2 1;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "C";
.port_info 3 /INPUT 1 "D";
.port_info 4 /OUTPUT 1 "F";
o000001e0df496fd8 .functor BUFZ 1, C4<z>; HiZ drive
L_000001e0df462f70 .functor NOT 1, o000001e0df496fd8, C4<0>, C4<0>, C4<0>;
o000001e0df497098 .functor BUFZ 1, C4<z>; HiZ drive
o000001e0df4970f8 .functor BUFZ 1, C4<z>; HiZ drive
L_000001e0df64aa10 .functor AND 1, L_000001e0df462f70, o000001e0df497098, o000001e0df4970f8, C4<1>;
L_000001e0df64aa80 .functor NOT 1, o000001e0df497098, C4<0>, C4<0>, C4<0>;
o000001e0df497188 .functor BUFZ 1, C4<z>; HiZ drive
L_000001e0df64aaf0 .functor AND 1, o000001e0df496fd8, o000001e0df497188, C4<1>, C4<1>;
L_000001e0df64ab60 .functor NOT 1, o000001e0df4970f8, C4<0>, C4<0>, C4<0>;
L_000001e0df64abd0 .functor AND 1, L_000001e0df64ab60, o000001e0df497188, C4<1>, C4<1>;
L_000001e0df64ac40 .functor OR 1, L_000001e0df64aa10, L_000001e0df64aa80, L_000001e0df64aaf0, L_000001e0df64abd0;
v000001e0df462b30_0 .net "A", 0 0, o000001e0df496fd8; 0 drivers
v000001e0df462d50_0 .net "AD", 0 0, L_000001e0df64aaf0; 1 drivers
v000001e0df462770_0 .net "An", 0 0, L_000001e0df462f70; 1 drivers
v000001e0df462810_0 .net "AnBC", 0 0, L_000001e0df64aa10; 1 drivers
v000001e0df4628b0_0 .net "B", 0 0, o000001e0df497098; 0 drivers
v000001e0df64ed90_0 .net "Bn", 0 0, L_000001e0df64aa80; 1 drivers
v000001e0df64ee30_0 .net "C", 0 0, o000001e0df4970f8; 0 drivers
v000001e0df64eed0_0 .net "Cn", 0 0, L_000001e0df64ab60; 1 drivers
v000001e0df64a840_0 .net "CnD", 0 0, L_000001e0df64abd0; 1 drivers
v000001e0df64a970_0 .net "D", 0 0, o000001e0df497188; 0 drivers
v000001e0df492660_0 .net "F", 0 0, L_000001e0df64ac40; 1 drivers
# The file index is used to find the file name in the following table.
:file_names 3;
"N/A";
"<interactive>";
".\f_lab2.v";

32
lab2_prep/src/tb.v Normal file
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@ -0,0 +1,32 @@
module tb();
reg r1, r2, r3, r4;
wire w1;
lab2 uut(
.A(r1),
.B(r2),
.C(r3),
.D(r4),
.F(w1)
);
// test uut(r1, r2, w1, w2, w3);
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50;
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50;
$display(w1);
end
endmodule