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4-bit ALU

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k0rrluna
2024-12-14 05:00:35 +03:00
parent cd93206ad4
commit cbf97501ea
16 changed files with 1781 additions and 0 deletions
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project/opCodeTB.v Normal file
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module opCodeTB();
reg A, B, C;
wire [7:0] opCode;
opCode uut (
.A(A),
.B(B),
.C(C),
.opCode(opCode)
);
initial begin
$dumpfile("opCode.vcd");
$dumpvars;
A = 1'b0; B = 1'b0; C = 1'b0; #3;
A = 1'b0; B = 1'b0; C = 1'b1; #3;
A = 1'b0; B = 1'b1; C = 1'b0; #3;
A = 1'b0; B = 1'b1; C = 1'b1; #3;
A = 1'b1; B = 1'b0; C = 1'b0; #3;
A = 1'b1; B = 1'b0; C = 1'b1; #3;
A = 1'b1; B = 1'b1; C = 1'b0; #3;
A = 1'b1; B = 1'b1; C = 1'b1; #3;
$finish;
end
endmodule