4-bit ALU

2024-12-14 05:00:35 +03:00
parent cd93206ad4
commit cbf97501ea
16 changed files with 1781 additions and 0 deletions
--- a/project/fulladder.v
+++ b/project/fulladder.v
@ -0,0 +1,12 @@
+module fulladder (
+    input A, B, Carry,
+    output Sum, CarryO
+);
+
+wire xor1, and1, and2;
+
+halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
+halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
+or o1 (CarryO, and1, and2);
+
+endmodule