merge
This commit is contained in:
commit
6b83c0f2e7
@ -1,25 +0,0 @@
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|||||||
<?xml version="1" encoding="UTF-8"?>
|
|
||||||
<!DOCTYPE gowin-fpga-project>
|
|
||||||
<Project>
|
|
||||||
<Template>FPGA</Template>
|
|
||||||
<Version>5</Version>
|
|
||||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
|
||||||
<FileList>
|
|
||||||
<File path="src/ALU.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/BinaryToBCD.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/addition.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/arithmeticUnit.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/bttn.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/dabble.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/fulladder.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/fullsubtraction.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/halfadder.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/halfsubtraction.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/logicUnit.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/multiplier.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/opCode.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/selector.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/subtraction.v" type="file.verilog" enable="1"/>
|
|
||||||
<File path="src/bttn.cst" type="file.cst" enable="1"/>
|
|
||||||
</FileList>
|
|
||||||
</Project>
|
|
@ -7,6 +7,8 @@
|
|||||||
<Process ID="Pnr" State="2"/>
|
<Process ID="Pnr" State="2"/>
|
||||||
<Process ID="Gao" State="2"/>
|
<Process ID="Gao" State="2"/>
|
||||||
<Process ID="Rtl_Gao" State="2"/>
|
<Process ID="Rtl_Gao" State="2"/>
|
||||||
|
<Process ID="Gvio" State="2"/>
|
||||||
|
<Process ID="Place" State="2"/>
|
||||||
</FlowState>
|
</FlowState>
|
||||||
<ResultFileList>
|
<ResultFileList>
|
||||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
|
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/bttn.vg"/>
|
||||||
@ -20,5 +22,10 @@
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|||||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
|
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/bttn_syn.rpt.html"/>
|
||||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
|
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/bttn_syn_rsc.xml"/>
|
||||||
</ResultFileList>
|
</ResultFileList>
|
||||||
|
<<<<<<< HEAD
|
||||||
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000011201000027fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff000000c000fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff000000bc00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff000000ea00ffffff0000000300000ab000000145fc0100000001fc0000000000000ab0000000e700fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000e700ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000ffffffff0100000275ffffffff0000000000000000</Ui>
|
<Ui>000000ff00000001fd00000002000000000000018e0000051efc0200000001fc000000630000051e0000011201000027fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff000000c000fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff000000bc00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff000000ea00ffffff0000000300000ab000000145fc0100000001fc0000000000000ab0000000e700fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000e700ffffff0000091a0000051e00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000ffffffff0100000275ffffffff0000000000000000</Ui>
|
||||||
|
=======
|
||||||
|
<Ui>000000ff00000001fd00000002000000000000018e0000025dfc0200000001fc000000370000025d0000000000fffffffaffffffff0200000004fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000000000030000078000000145fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000005ee0000025d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f00630065007300730100000245ffffffff0000000000000000</Ui>
|
||||||
|
<FpUi></FpUi>
|
||||||
|
>>>>>>> 15916a2c534beff06a16239dd4912b40b7f837b6
|
||||||
</UserConfig>
|
</UserConfig>
|
||||||
|
@ -4,6 +4,7 @@
|
|||||||
"CPU" : false,
|
"CPU" : false,
|
||||||
"CRC_CHECK" : true,
|
"CRC_CHECK" : true,
|
||||||
"Clock_Route_Order" : 0,
|
"Clock_Route_Order" : 0,
|
||||||
|
"Convert_SDP32_36_to_SDP16_18" : true,
|
||||||
"Correct_Hold_Violation" : true,
|
"Correct_Hold_Violation" : true,
|
||||||
"DONE" : false,
|
"DONE" : false,
|
||||||
"DOWNLOAD_SPEED" : "default",
|
"DOWNLOAD_SPEED" : "default",
|
||||||
@ -18,7 +19,7 @@
|
|||||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||||
"Enable_DSRM" : false,
|
"Enable_DSRM" : false,
|
||||||
"FORMAT" : "binary",
|
"FORMAT" : "binary",
|
||||||
"FREQUENCY_DIVIDER" : "",
|
"FREQUENCY_DIVIDER" : "1",
|
||||||
"Generate_Constraint_File_of_Ports" : false,
|
"Generate_Constraint_File_of_Ports" : false,
|
||||||
"Generate_IBIS_File" : false,
|
"Generate_IBIS_File" : false,
|
||||||
"Generate_Plain_Text_Timing_Report" : false,
|
"Generate_Plain_Text_Timing_Report" : false,
|
||||||
@ -31,6 +32,8 @@
|
|||||||
"HOTBOOT" : false,
|
"HOTBOOT" : false,
|
||||||
"I2C" : false,
|
"I2C" : false,
|
||||||
"I2C_SLAVE_ADDR" : "00",
|
"I2C_SLAVE_ADDR" : "00",
|
||||||
|
"INCREMENTAL_PLACE_AND_ROUTING" : "0",
|
||||||
|
"INCREMENTAL_PLACE_ONLY" : "0",
|
||||||
"IncludePath" : [
|
"IncludePath" : [
|
||||||
|
|
||||||
],
|
],
|
||||||
@ -78,6 +81,7 @@
|
|||||||
"TopModule" : "",
|
"TopModule" : "",
|
||||||
"USERCODE" : "default",
|
"USERCODE" : "default",
|
||||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||||
|
"VCC" : "1.0",
|
||||||
"VCCAUX" : 3.3,
|
"VCCAUX" : 3.3,
|
||||||
"VCCX" : "3.3",
|
"VCCX" : "3.3",
|
||||||
"VHDL_Standard" : "VHDL_Std_1993",
|
"VHDL_Standard" : "VHDL_Std_1993",
|
||||||
|
@ -1,130 +0,0 @@
|
|||||||
GowinSynthesis start
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|
||||||
Running parser ...
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v'
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|
||||||
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v'
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|
||||||
Compiling module 'bttn'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":1)
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|
||||||
Compiling module 'ALU'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":1)
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|
||||||
Compiling module 'opCode'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v":1)
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|
||||||
Compiling module 'arithmeticUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":1)
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|
||||||
Compiling module 'addition'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":1)
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|
||||||
Compiling module 'fulladder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":1)
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|
||||||
Compiling module 'halfadder'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v":1)
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|
||||||
Compiling module 'subtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":1)
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|
||||||
Compiling module 'fullsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":1)
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|
||||||
Compiling module 'halfsubtraction'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v":1)
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|
||||||
Compiling module 'logicUnit'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v":1)
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|
||||||
Compiling module 'multiplier'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":1)
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|
||||||
Compiling module 'BinaryToBCD'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":1)
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|
||||||
Compiling module 'dabble'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v":1)
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|
||||||
Compiling module 'selector'("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v":1)
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|
||||||
NOTE (EX0101) : Current top module is "bttn"
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|
||||||
[5%] Running netlist conversion ...
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|
||||||
Running device independent optimization ...
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|
||||||
[10%] Optimizing Phase 0 completed
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|
||||||
[15%] Optimizing Phase 1 completed
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|
||||||
[25%] Optimizing Phase 2 completed
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|
||||||
Running inference ...
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|
||||||
[30%] Inferring Phase 0 completed
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|
||||||
[40%] Inferring Phase 1 completed
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|
||||||
[50%] Inferring Phase 2 completed
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|
||||||
[55%] Inferring Phase 3 completed
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|
||||||
Running technical mapping ...
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|
||||||
[60%] Tech-Mapping Phase 0 completed
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|
||||||
[65%] Tech-Mapping Phase 1 completed
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|
||||||
[75%] Tech-Mapping Phase 2 completed
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|
||||||
[80%] Tech-Mapping Phase 3 completed
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|
||||||
[90%] Tech-Mapping Phase 4 completed
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|
||||||
WARN (NL0002) : The module "ALU" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v":13)
|
|
||||||
WARN (NL0002) : The module "arithmeticUnit" instantiated to "aU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":20)
|
|
||||||
WARN (NL0002) : The module "addition" instantiated to "a1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":13)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "subtraction" instantiated to "s1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v":14)
|
|
||||||
WARN (NL0002) : The module "fullsubtraction" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":11)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
|
|
||||||
WARN (NL0002) : The module "fullsubtraction" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":12)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
|
|
||||||
WARN (NL0002) : The module "fullsubtraction" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":13)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
|
|
||||||
WARN (NL0002) : The module "fullsubtraction" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v":14)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":8)
|
|
||||||
WARN (NL0002) : The module "halfsubtraction" instantiated to "hf2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v":9)
|
|
||||||
WARN (NL0002) : The module "BinaryToBCD" instantiated to "btod1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":76)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d1t" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":21)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d2u" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":30)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d3v" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":39)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d4w" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":48)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d5x" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":57)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d6y" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":66)
|
|
||||||
WARN (NL0002) : The module "dabble" instantiated to "d7z" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v":75)
|
|
||||||
WARN (NL0002) : The module "logicUnit" instantiated to "lU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":21)
|
|
||||||
WARN (NL0002) : The module "multiplier" instantiated to "mU" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":22)
|
|
||||||
WARN (NL0002) : The module "addition" instantiated to "add0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":33)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "addition" instantiated to "add1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":49)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "addition" instantiated to "add2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v":65)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f0" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":11)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":12)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":13)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "fulladder" instantiated to "f3" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v":14)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h1" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":8)
|
|
||||||
WARN (NL0002) : The module "halfadder" instantiated to "h2" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v":9)
|
|
||||||
WARN (NL0002) : The module "opCode" instantiated to "opCd" is swept in optimizing("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v":18)
|
|
||||||
[95%] Generate netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
|
|
||||||
[100%] Generate report file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn_syn.rpt.html" completed
|
|
||||||
GowinSynthesis finish
|
|
@ -1,33 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<!DOCTYPE gowin-synthesis-project>
|
|
||||||
<Project>
|
|
||||||
<Version>beta</Version>
|
|
||||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
|
||||||
<FileList>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v" type="verilog"/>
|
|
||||||
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v" type="verilog"/>
|
|
||||||
</FileList>
|
|
||||||
<OptionList>
|
|
||||||
<Option type="disable_insert_pad" value="0"/>
|
|
||||||
<Option type="global_freq" value="100.000"/>
|
|
||||||
<Option type="looplimit" value="2000"/>
|
|
||||||
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"/>
|
|
||||||
<Option type="print_all_synthesis_warning" value="0"/>
|
|
||||||
<Option type="ram_rw_check" value="0"/>
|
|
||||||
<Option type="verilog_language" value="verilog-2001"/>
|
|
||||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
|
||||||
</OptionList>
|
|
||||||
</Project>
|
|
@ -1,465 +0,0 @@
|
|||||||
//
|
|
||||||
//Written by GowinSynthesis
|
|
||||||
//Tool Version "V1.9.9.03 Education (64-bit)"
|
|
||||||
//Mon Jan 20 17:48:05 2025
|
|
||||||
|
|
||||||
//Source file index table:
|
|
||||||
//file0 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v"
|
|
||||||
//file1 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v"
|
|
||||||
//file2 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v"
|
|
||||||
//file3 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v"
|
|
||||||
//file4 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v"
|
|
||||||
//file5 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v"
|
|
||||||
//file6 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v"
|
|
||||||
//file7 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v"
|
|
||||||
//file8 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v"
|
|
||||||
//file9 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v"
|
|
||||||
//file10 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v"
|
|
||||||
//file11 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v"
|
|
||||||
//file12 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v"
|
|
||||||
//file13 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v"
|
|
||||||
//file14 "\//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v"
|
|
||||||
`pragma protect begin_protected
|
|
||||||
`pragma protect version="2.3"
|
|
||||||
`pragma protect author="default"
|
|
||||||
`pragma protect author_info="default"
|
|
||||||
`pragma protect encrypt_agent="GOWIN"
|
|
||||||
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
|
|
||||||
|
|
||||||
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
|
|
||||||
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
|
|
||||||
`pragma protect key_block
|
|
||||||
iI5y7361qCSMp3g5erD4GmepNu30IMQTBS61iw7VMIQyqSjnzq+9IqxyIZAW68JoHNnT3d00Qbza
|
|
||||||
jePErhV/ikZszW8FS8kjP8+BcD65CFJz87FpWez5gLGPxxgUqm6SniOCgdDC0FL89jDWhX5HNzYn
|
|
||||||
a+1tpRG0nU2+sH5QywrEE3hMrgpNL1kb5WmdY07RQpnQwxnsPZhBY9nHuJWUqYy6W73uVkDrGicZ
|
|
||||||
o9bJWbjs7PpDLen5/5X2F2ghr+Mr25wRKaCsGNX9+VtGQBXQjwS/Zi2hmMgvEKPfLyJtVZb8lEXV
|
|
||||||
t7Zf3CNexgJWAnQGN7CfOaxH/yrKTBWTu6YfzQ==
|
|
||||||
|
|
||||||
`pragma protect encoding=(enctype="base64", line_length=76, bytes=24000)
|
|
||||||
`pragma protect data_keyowner="default-ip-vendor"
|
|
||||||
`pragma protect data_keyname="default-ip-key"
|
|
||||||
`pragma protect data_method="aes128-cfb"
|
|
||||||
`pragma protect data_block
|
|
||||||
93ziQRuZMaVBcQsvnLtb8Yw7rS1shOC1VCQZW92lhqesYTj5LrdKRr2tLCGjlD0vDghAHdgl883l
|
|
||||||
VmuPi+r4QSr2xAfXqnP4kRb16IlMIX+sdf0qRwTWXGoMA6A6N/7KdUcJz3hAIJb0WsDNWWSX5TBM
|
|
||||||
dPTWp+qfLrvjCkVhgDboEyWq4egjVVJdH37UbK0A9wbxVGiwqwIuKnnswrublHyFpP2LxrrP4cAy
|
|
||||||
aJm9GKUNmfy+GgFGd8k6wsgF1X7e9hrQmvCYPOTDJqn2Za+cf1Vu9vDIJToLklklU3OTbo8JzNkQ
|
|
||||||
WxcFtLJRFEUigBxsSWpmlzcLojZ6bJJwISuu9Nug2Ph/N/HTZLOk0nbJ2R+teuMdHvRqoe9RURPi
|
|
||||||
FbB+px7pAnOf5F6163AhpkJgt5XkSqxWXXQgQ4+RJka1e4Qxadn2rZk4Munb2pwOBbRQPR0d/oQt
|
|
||||||
OUhJKZvLpT8m6HMkHYqgtt53QuEr+tap8XO7m7g0omnJozJzmAL0ETUVYGWI5Z2FuKtSCYJvhLvI
|
|
||||||
Tzgzaduie2y/aFEfSv4PMRI9JoRyIjw4Wr8r22VfM7tX52QJuM8Qq6d2BlzhVrVTL7Z6Clc9EOCA
|
|
||||||
aJ3hsiG7iw2FtL1ae0WSlWAaFTGA4Xt80ZLy/yXNby2aenwZkxOss8PdAFv9IA5zH+LIcAplVN2H
|
|
||||||
Gay2T5IOpgwGPLC+AKHkIkKDsoo/aC51wVKFlw1R2eq+X+0X6b6Cem7wSVsZuRttwBgavhjW0r7G
|
|
||||||
p/+miD6jZOpv7Xuiwzsg9NXGgUqjed48fJdcyU69KDSpZZE0WzKWZZbizcEN1vZ+YyKYLNtKlGd5
|
|
||||||
ttLPs+ZE4AOsCYHVz0ZpsscHhDzm9tn2CsRshlQreHxcXqmm6QGA/hhYk6YlTEVngcn17YHS5jxh
|
|
||||||
IU5Ou57Gdz+Z8MEexDlMNDMkWfCpTpc/pdplkkmA2yAYC1LWb+JAXoRlep5IuCnv/JDA8xsIseDa
|
|
||||||
T26cVaR7B0Fc2S0Ui5H+dbbsKHMOBM7rEZ3Iqunwgwcc/kPLevM6C1ANBfn8IR4yrZ0J+d5f6SUA
|
|
||||||
YHayFX8JGGKPDzrQWnASTCUu5KrUGSQl3S0QFNLESgH4EOURAjUCNzuZzPcg8/TQdmUwR8e89VnN
|
|
||||||
09t8Nh4xnTvDzomAT5LYwvJJ5cUyZUdg56VZoOLup63fg7S3bAg7b6bcMpgtt/g11MBbiMDbVLN5
|
|
||||||
ZbhMkEMYv5MB/akGGwOShXxljVJiGFAb2vsTO2XAVJi2u32W7pBJCc68GgREgOoHc4uvvBldfCvB
|
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||||||
sRRv
|
|
||||||
`pragma protect end_protected
|
|
@ -1,189 +0,0 @@
|
|||||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
||||||
<html>
|
|
||||||
<head>
|
|
||||||
<title>synthesis Report</title>
|
|
||||||
<style type="text/css">
|
|
||||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
|
||||||
div#main_wrapper{ width: 100%; }
|
|
||||||
div#content { margin-left: 350px; margin-right: 30px; }
|
|
||||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
|
||||||
div#catalog ul { list-style-type: none; }
|
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div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
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div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
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div#catalog a:visited { color: #0084ff; }
|
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div#catalog a:hover { color: #fff; background: #0084ff; }
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||||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
|
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
|
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||||||
table, th, td { border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
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table.detail_table td.label { min-width: 100px; width: 8%;}
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</style>
|
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</head>
|
|
||||||
<body>
|
|
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<div id="main_wrapper">
|
|
||||||
<div id="catalog_wrapper">
|
|
||||||
<div id="catalog">
|
|
||||||
<ul>
|
|
||||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
|
||||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
|
||||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
|
||||||
<ul>
|
|
||||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
|
||||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
</ul>
|
|
||||||
</div><!-- catalog -->
|
|
||||||
</div><!-- catalog_wrapper -->
|
|
||||||
<div id="content">
|
|
||||||
<h1><a name="about">Synthesis Messages</a></h1>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Report Title</td>
|
|
||||||
<td>GowinSynthesis Report</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Design File</td>
|
|
||||||
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\ALU.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\BinaryToBCD.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\addition.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\arithmeticUnit.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\dabble.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fulladder.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\fullsubtraction.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfadder.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\halfsubtraction.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\logicUnit.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\multiplier.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\opCode.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\selector.v<br>
|
|
||||||
\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\subtraction.v<br>
|
|
||||||
</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">GowinSynthesis Constraints File</td>
|
|
||||||
<td>---</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Tool Version</td>
|
|
||||||
<td>V1.9.9.03 Education (64-bit)</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Part Number</td>
|
|
||||||
<td>GW2A-LV18PG256C8/I7</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Device</td>
|
|
||||||
<td>GW2A-18</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Device Version</td>
|
|
||||||
<td>C</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Created Time</td>
|
|
||||||
<td>Mon Jan 20 17:48:06 2025
|
|
||||||
</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Legal Announcement</td>
|
|
||||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h1><a name="summary">Synthesis Details</a></h1>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Top Level Module</td>
|
|
||||||
<td>bttn</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Synthesis Process</td>
|
|
||||||
<td>Running parser:<br/> CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.312s, Peak memory usage = 441.031MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 441.031MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 441.031MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 441.031MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 441.031MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 441.031MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 441.031MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 441.031MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 441.031MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 441.031MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 441.031MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 441.031MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 441.031MB<br/>Generate output files:<br/> CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 441.031MB<br/></td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Total Time and Memory Usage</td>
|
|
||||||
<td>CPU time = 0h 0m 2s, Elapsed time = 0h 0m 3s, Peak memory usage = 441.031MB</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h1><a name="resource">Resource</a></h1>
|
|
||||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label"><b>Resource</b></td>
|
|
||||||
<td><b>Usage</b></td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label"><b>I/O Port </b></td>
|
|
||||||
<td>28</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label"><b>I/O Buf </b></td>
|
|
||||||
<td>28</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">    IBUF</td>
|
|
||||||
<td>14</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">    OBUF</td>
|
|
||||||
<td>14</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label"><b>LUT </b></td>
|
|
||||||
<td>141</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">    LUT2</td>
|
|
||||||
<td>16</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">    LUT3</td>
|
|
||||||
<td>36</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">    LUT4</td>
|
|
||||||
<td>89</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label"><b>Resource</b></td>
|
|
||||||
<td><b>Usage</b></td>
|
|
||||||
<td><b>Utilization</b></td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Logic</td>
|
|
||||||
<td>141(141 LUT, 0 ALU) / 20736</td>
|
|
||||||
<td><1%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Register</td>
|
|
||||||
<td>0 / 16173</td>
|
|
||||||
<td>0%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">  --Register as Latch</td>
|
|
||||||
<td>0 / 16173</td>
|
|
||||||
<td>0%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">  --Register as FF</td>
|
|
||||||
<td>0 / 16173</td>
|
|
||||||
<td>0%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">BSRAM</td>
|
|
||||||
<td>0 / 46</td>
|
|
||||||
<td>0%</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
</div><!-- content -->
|
|
||||||
</div><!-- main_wrapper -->
|
|
||||||
</body>
|
|
||||||
</html>
|
|
@ -1,56 +0,0 @@
|
|||||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
||||||
<html>
|
|
||||||
<head>
|
|
||||||
<title>Hierarchy Module Resource</title>
|
|
||||||
<style type="text/css">
|
|
||||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
|
||||||
div#main_wrapper{ width: 100%; }
|
|
||||||
h1 {text-align: center; }
|
|
||||||
h1 {margin-top: 36px; }
|
|
||||||
table, th, td { border: 1px solid #aaa; }
|
|
||||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
|
||||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
|
||||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
|
||||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
|
||||||
</style>
|
|
||||||
</head>
|
|
||||||
<body>
|
|
||||||
<div id="main_wrapper">
|
|
||||||
<div id="content">
|
|
||||||
<h1>Hierarchy Module Resource</h1>
|
|
||||||
<table>
|
|
||||||
<tr>
|
|
||||||
<th class="label">MODULE NAME</th>
|
|
||||||
<th class="label">REG NUMBER</th>
|
|
||||||
<th class="label">ALU NUMBER</th>
|
|
||||||
<th class="label">LUT NUMBER</th>
|
|
||||||
<th class="label">DSP NUMBER</th>
|
|
||||||
<th class="label">BSRAM NUMBER</th>
|
|
||||||
<th class="label">SSRAM NUMBER</th>
|
|
||||||
<th class="label">ROM16 NUMBER</th>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">bttn (//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">13</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
</tr>
|
|
||||||
<td class="label">    |--s1
|
|
||||||
(//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v)</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">128</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
<td align = "center">-</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
</div><!-- content -->
|
|
||||||
</div><!-- main_wrapper -->
|
|
||||||
</body>
|
|
||||||
</html>
|
|
@ -1,4 +0,0 @@
|
|||||||
<?xml version="1.0" encoding="UTF-8"?>
|
|
||||||
<Module name="bttn" Lut="13" T_Lut="141(13)">
|
|
||||||
<SubModule name="s1" Lut="128" T_Lut="128(128)"/>
|
|
||||||
</Module>
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -1,29 +0,0 @@
|
|||||||
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg"
|
|
||||||
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg" completed
|
|
||||||
Processing netlist completed
|
|
||||||
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst"
|
|
||||||
Physical Constraint parsed completed
|
|
||||||
Running placement......
|
|
||||||
[10%] Placement Phase 0 completed
|
|
||||||
[20%] Placement Phase 1 completed
|
|
||||||
[30%] Placement Phase 2 completed
|
|
||||||
[50%] Placement Phase 3 completed
|
|
||||||
Running routing......
|
|
||||||
[60%] Routing Phase 0 completed
|
|
||||||
[70%] Routing Phase 1 completed
|
|
||||||
[80%] Routing Phase 2 completed
|
|
||||||
[90%] Routing Phase 3 completed
|
|
||||||
Running timing analysis......
|
|
||||||
[95%] Timing analysis completed
|
|
||||||
Placement and routing completed
|
|
||||||
Bitstream generation in progress......
|
|
||||||
Bitstream generation completed
|
|
||||||
Running power analysis......
|
|
||||||
[100%] Power analysis completed
|
|
||||||
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.power.html" completed
|
|
||||||
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.pin.html" completed
|
|
||||||
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.html" completed
|
|
||||||
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.rpt.txt" completed
|
|
||||||
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\bttn.tr.html" completed
|
|
||||||
Mon Jan 20 17:48:16 2025
|
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
@ -1,269 +0,0 @@
|
|||||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
||||||
<html>
|
|
||||||
<head>
|
|
||||||
<title>Power Analysis Report</title>
|
|
||||||
<style type="text/css">
|
|
||||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
|
||||||
div#main_wrapper { width: 100%; }
|
|
||||||
div#content { margin-left: 350px; margin-right: 30px; }
|
|
||||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
|
||||||
div#catalog ul { list-style-type: none; }
|
|
||||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
|
||||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
|
||||||
div#catalog a:visited { color: #0084ff; }
|
|
||||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
|
||||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
|
||||||
h1, h3 { text-align: center; }
|
|
||||||
h1 {margin-top: 50px; }
|
|
||||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
|
||||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
|
||||||
th, td { padding: 5px 5px 5px 5px; }
|
|
||||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
|
||||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
|
||||||
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
|
||||||
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
|
||||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
|
||||||
</style>
|
|
||||||
</head>
|
|
||||||
<body>
|
|
||||||
<div id="main_wrapper">
|
|
||||||
<div id="catalog_wrapper">
|
|
||||||
<div id="catalog">
|
|
||||||
<ul>
|
|
||||||
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
|
|
||||||
<ul>
|
|
||||||
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
|
|
||||||
<ul>
|
|
||||||
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
|
|
||||||
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
|
|
||||||
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
|
|
||||||
<ul>
|
|
||||||
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
|
|
||||||
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
|
|
||||||
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
</ul>
|
|
||||||
</div><!-- catalog -->
|
|
||||||
</div><!-- catalog_wrapper -->
|
|
||||||
<div id="content">
|
|
||||||
<h1><a name="Message">Power Messages</a></h1>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Report Title</td>
|
|
||||||
<td>Power Analysis Report</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Design File</td>
|
|
||||||
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Physical Constraints File</td>
|
|
||||||
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Timing Constraints File</td>
|
|
||||||
<td>---</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Tool Version</td>
|
|
||||||
<td>V1.9.9.03 Education (64-bit)</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Part Number</td>
|
|
||||||
<td>GW2A-LV18PG256C8/I7</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Device</td>
|
|
||||||
<td>GW2A-18</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Device Version</td>
|
|
||||||
<td>C</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Created Time</td>
|
|
||||||
<td>Mon Jan 20 17:48:13 2025
|
|
||||||
</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Legal Announcement</td>
|
|
||||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Configure_Info">Configure Information:</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Grade</td>
|
|
||||||
<td>Commercial</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Process</td>
|
|
||||||
<td>Typical</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Ambient Temperature</td>
|
|
||||||
<td>25.000
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Use Custom Theta JA</td>
|
|
||||||
<td>false</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Heat Sink</td>
|
|
||||||
<td>None</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Air Flow</td>
|
|
||||||
<td>LFM_0</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Use Custom Theta SA</td>
|
|
||||||
<td>false</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Board Thermal Model</td>
|
|
||||||
<td>None</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Use Custom Theta JB</td>
|
|
||||||
<td>false</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Related Vcd File</td>
|
|
||||||
<td></td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Related Saif File</td>
|
|
||||||
<td></td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Filter Glitches</td>
|
|
||||||
<td>false</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Default IO Toggle Rate</td>
|
|
||||||
<td>0.125</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Default Remain Toggle Rate</td>
|
|
||||||
<td>0.125</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h1><a name="Summary">Power Summary</a></h1>
|
|
||||||
<h2><a name="Power_Info">Power Information:</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Total Power (mW)</td>
|
|
||||||
<td>124.522</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Quiescent Power (mW)</td>
|
|
||||||
<td>121.169</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Dynamic Power (mW)</td>
|
|
||||||
<td>3.353</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Junction Temperature</td>
|
|
||||||
<td>28.987</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Theta JA</td>
|
|
||||||
<td>32.020</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Max Allowed Ambient Temperature</td>
|
|
||||||
<td>81.013</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Supply_Summary">Supply Information:</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Voltage Source</th>
|
|
||||||
<th class="label">Voltage</th>
|
|
||||||
<th class="label">Dynamic Current(mA)</th>
|
|
||||||
<th class="label">Quiescent Current(mA)</th>
|
|
||||||
<th class="label">Power(mW)</th>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>VCC</td>
|
|
||||||
<td>1.000</td>
|
|
||||||
<td>0.552</td>
|
|
||||||
<td>69.981</td>
|
|
||||||
<td>70.533</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>VCCX</td>
|
|
||||||
<td>3.300</td>
|
|
||||||
<td>0.552</td>
|
|
||||||
<td>15.000</td>
|
|
||||||
<td>51.322</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>VCCIO18</td>
|
|
||||||
<td>1.800</td>
|
|
||||||
<td>0.544</td>
|
|
||||||
<td>0.938</td>
|
|
||||||
<td>2.668</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h1><a name="Detail">Power Details</a></h1>
|
|
||||||
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Block Type</th>
|
|
||||||
<th class="label">Total Power(mW)</th>
|
|
||||||
<th class="label">Static Power(mW)</th>
|
|
||||||
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>IO</td>
|
|
||||||
<td>8.544
|
|
||||||
<td>5.191
|
|
||||||
<td>6.250
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Hierarchy Entity</th>
|
|
||||||
<th class="label">Total Power(mW)</th>
|
|
||||||
<th class="label">Block Dynamic Power(mW)</th>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>bttn</td>
|
|
||||||
<td>0.000</td>
|
|
||||||
<td>0.000(0.000)</td>
|
|
||||||
<tr>
|
|
||||||
<td>bttn/s1/</td>
|
|
||||||
<td>0.000</td>
|
|
||||||
<td>0.000(0.000)</td>
|
|
||||||
</table>
|
|
||||||
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Clock Domain</th>
|
|
||||||
<th class="label">Clock Frequency(Mhz)</th>
|
|
||||||
<th class="label">Total Dynamic Power(mW)</th>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>NO CLOCK DOMAIN</td>
|
|
||||||
<td>0.000</td>
|
|
||||||
<td>0.000</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
</div><!-- content -->
|
|
||||||
</div><!-- main_wrapper -->
|
|
||||||
</body>
|
|
||||||
</html>
|
|
File diff suppressed because it is too large
Load Diff
@ -1,366 +0,0 @@
|
|||||||
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
|
|
||||||
//All rights reserved.
|
|
||||||
|
|
||||||
|
|
||||||
1. PnR Messages
|
|
||||||
|
|
||||||
<Report Title>: PnR Report
|
|
||||||
<Design File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
|
|
||||||
<Physical Constraints File>: \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
|
|
||||||
<Timing Constraints File>: ---
|
|
||||||
<Tool Version>: V1.9.9.03 Education (64-bit)
|
|
||||||
<Part Number>: GW2A-LV18PG256C8/I7
|
|
||||||
<Device>: GW2A-18
|
|
||||||
<Device Version>: C
|
|
||||||
<Created Time>:Mon Jan 20 17:48:15 2025
|
|
||||||
|
|
||||||
|
|
||||||
2. PnR Details
|
|
||||||
|
|
||||||
Running placement:
|
|
||||||
Placement Phase 0: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.024s
|
|
||||||
Placement Phase 1: CPU time = 0h 0m 0.348s, Elapsed time = 0h 0m 0.348s
|
|
||||||
Placement Phase 2: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s
|
|
||||||
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
|
|
||||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
|
||||||
Running routing:
|
|
||||||
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
|
||||||
Routing Phase 1: CPU time = 0h 0m 0.173s, Elapsed time = 0h 0m 0.173s
|
|
||||||
Routing Phase 2: CPU time = 0h 0m 0.232s, Elapsed time = 0h 0m 0.231s
|
|
||||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
|
||||||
Total Routing: CPU time = 0h 0m 0.405s, Elapsed time = 0h 0m 0.404s
|
|
||||||
Generate output files:
|
|
||||||
CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
|
|
||||||
|
|
||||||
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 443MB
|
|
||||||
|
|
||||||
|
|
||||||
3. Resource Usage Summary
|
|
||||||
|
|
||||||
----------------------------------------------------------
|
|
||||||
Resources | Usage
|
|
||||||
----------------------------------------------------------
|
|
||||||
Logic | 141/20736 <1%
|
|
||||||
--LUT,ALU,ROM16 | 141(141 LUT, 0 ALU, 0 ROM16)
|
|
||||||
--SSRAM(RAM16) | 0
|
|
||||||
Register | 0/16173 0%
|
|
||||||
--Logic Register as Latch | 0/15552 0%
|
|
||||||
--Logic Register as FF | 0/15552 0%
|
|
||||||
--I/O Register as Latch | 0/621 0%
|
|
||||||
--I/O Register as FF | 0/621 0%
|
|
||||||
CLS | 75/10368 <1%
|
|
||||||
I/O Port | 28
|
|
||||||
I/O Buf | 28
|
|
||||||
--Input Buf | 14
|
|
||||||
--Output Buf | 14
|
|
||||||
--Inout Buf | 0
|
|
||||||
IOLOGIC | 0%
|
|
||||||
BSRAM | 0%
|
|
||||||
DSP | 0%
|
|
||||||
PLL | 0/4 0%
|
|
||||||
DCS | 0/8 0%
|
|
||||||
DQCE | 0/24 0%
|
|
||||||
OSC | 0/1 0%
|
|
||||||
CLKDIV | 0/8 0%
|
|
||||||
DLLDLY | 0/8 0%
|
|
||||||
DQS | 0/9 0%
|
|
||||||
DHCEN | 0/16 0%
|
|
||||||
==========================================================
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
4. I/O Bank Usage Summary
|
|
||||||
|
|
||||||
-----------------------
|
|
||||||
I/O Bank | Usage
|
|
||||||
-----------------------
|
|
||||||
bank 0 | 1/29(3%)
|
|
||||||
bank 1 | 5/20(25%)
|
|
||||||
bank 2 | 2/20(10%)
|
|
||||||
bank 3 | 8/32(25%)
|
|
||||||
bank 4 | 2/36(5%)
|
|
||||||
bank 5 | 0/36(0%)
|
|
||||||
bank 6 | 2/18(11%)
|
|
||||||
bank 7 | 8/16(50%)
|
|
||||||
=======================
|
|
||||||
|
|
||||||
|
|
||||||
5. Global Clock Usage Summary
|
|
||||||
|
|
||||||
-------------------------------
|
|
||||||
Global Clock | Usage
|
|
||||||
-------------------------------
|
|
||||||
PRIMARY | 0/8(0%)
|
|
||||||
LW | 0/8(0%)
|
|
||||||
GCLK_PIN | 1/8(13%)
|
|
||||||
PLL | 0/4(0%)
|
|
||||||
CLKDIV | 0/8(0%)
|
|
||||||
DLLDLY | 0/8(0%)
|
|
||||||
===============================
|
|
||||||
|
|
||||||
|
|
||||||
6. Global Clock Signals
|
|
||||||
|
|
||||||
-------------------------------------------
|
|
||||||
Signal | Global Clock | Location
|
|
||||||
-------------------------------------------
|
|
||||||
===========================================
|
|
||||||
|
|
||||||
|
|
||||||
7. Pinout by Port Name
|
|
||||||
|
|
||||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
|
|
||||||
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
A[0] | | A11/7 | Y | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
A[1] | | N6/3 | Y | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
A[2] | | E15/1 | Y | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A[3] | | L9/3 | Y | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
B[0] | | B11/7 | Y | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
B[1] | | D11/7 | Y | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
B[2] | | N7/3 | Y | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
B[3] | | N8/3 | Y | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
opCodeA[0] | | T5/4 | Y | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
opCodeA[1] | | T4/4 | Y | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
opCodeA[2] | | E8/6 | Y | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
select[0] | | A15/7 | Y | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
select[1] | | A14/7 | Y | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
Cin | | E9/6 | Y | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
leds[0] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
leds[1] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
Y[0] | | P6/3 | Y | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[1] | | T7/3 | Y | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[2] | | P8/3 | Y | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[3] | | P9/3 | Y | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[4] | | T11/2 | Y | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[5] | | T12/2 | Y | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[6] | | M14/1 | Y | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
Y[7] | | J14/0 | Y | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
Y[8] | | D14/1 | Y | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
Y[9] | | B14/7 | Y | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[10] | | B13/7 | Y | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
Y[11] | | B12/7 | Y | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
===================================================================================================================================================================================================================
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
8. All Package Pins
|
|
||||||
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J14/0 | Y[7] | out | IOT22[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L16/1 | leds[0] | out | IOT34[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
L14/1 | leds[1] | out | IOT34[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M14/1 | Y[6] | out | IOT40[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D14/1 | Y[8] | out | IOT44[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
E15/1 | A[2] | in | IOT44[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T4/4 | opCodeA[1] | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T5/4 | opCodeA[0] | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
B14/7 | Y[9] | out | IOL2[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
A15/7 | select[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B12/7 | Y[11] | out | IOL7[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
B13/7 | Y[10] | out | IOL8[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
A14/7 | select[1] | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B11/7 | B[0] | in | IOL13[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A11/7 | A[0] | in | IOL15[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D11/7 | B[1] | in | IOL22[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E9/6 | Cin | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E8/6 | opCodeA[2] | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T12/2 | Y[5] | out | IOR17[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T11/2 | Y[4] | out | IOR24[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
|
||||||
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T7/3 | Y[1] | out | IOR29[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P9/3 | Y[3] | out | IOR38[B] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N8/3 | B[3] | in | IOR40[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
L9/3 | A[3] | in | IOR40[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
P8/3 | Y[2] | out | IOR42[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N7/3 | B[2] | in | IOR47[B] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
N6/3 | A[1] | in | IOR51[A] | LVCMOS18 | NA | NONE | ON | NONE | NA | NA | OFF | NA | 1.8
|
|
||||||
P6/3 | Y[0] | out | IOR53[A] | LVCMOS18 | 8 | NONE | NA | NA | OFF | NA | OFF | NA | 1.8
|
|
||||||
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
|
||||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
||||||
========================================================================================================================================================================================
|
|
||||||
|
|
||||||
|
|
@ -1,10 +0,0 @@
|
|||||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
||||||
<html>
|
|
||||||
<head>
|
|
||||||
<title>Timing Analysis Report</title>
|
|
||||||
</head>
|
|
||||||
<frameset cols="20%, 80%">
|
|
||||||
<frame src="bttn_tr_cata.html" name="cataFrame" />
|
|
||||||
<frame src="bttn_tr_content.html" name="mainFrame"/>
|
|
||||||
</frameset>
|
|
||||||
</html>
|
|
@ -1,132 +0,0 @@
|
|||||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
||||||
<html>
|
|
||||||
<head>
|
|
||||||
<title>Timing Report Navigation</title>
|
|
||||||
<style type="text/css">
|
|
||||||
@import url(../temp/style.css);
|
|
||||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
|
||||||
div#catalog_wrapper { width: 100%; }
|
|
||||||
div#catalog ul { list-style: none; margin-left: -15px; }
|
|
||||||
div#catalog ul li { margin: 3px 0 3px 0; text-align: left; color: #0084ff; white-space: nowrap; word-break: keep-all; }
|
|
||||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 4px; margin: 0 0 0 0; }
|
|
||||||
div#catalog a:visited { color: #0084ff; }
|
|
||||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
|
||||||
div.triangle_fake, div.triangle { display: inline-block; cursor: pointer; width: 8px; height: 0; border-top: 5px solid transparent; border-bottom: 5px solid transparent; }
|
|
||||||
div.triangle_fake { border-left: 5px solid transparent; }
|
|
||||||
div.triangle { border-left: 5px solid #0084ff; }
|
|
||||||
div.triangle:hover { border-left-color: #000; }
|
|
||||||
</style>
|
|
||||||
<script>
|
|
||||||
function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.length;i++){if(childs[i].tagName=="UL"){if(childs[i].style.display=="none"){childs[i].style.display="block"}else{childs[i].style.display="none"}}}};
|
|
||||||
</script>
|
|
||||||
</head>
|
|
||||||
<body>
|
|
||||||
<div id="catalog_wrapper">
|
|
||||||
<div id="catalog">
|
|
||||||
<ul>
|
|
||||||
<!-- messages begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
|
|
||||||
<!-- messages end-->
|
|
||||||
<!-- summaries begin-->
|
|
||||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
|
|
||||||
<ul>
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
<!-- summaries end-->
|
|
||||||
<!-- details begin-->
|
|
||||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
|
|
||||||
<ul>
|
|
||||||
<!--All_Path_Slack_Table begin-->
|
|
||||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
|
|
||||||
<ul>
|
|
||||||
<!--Setup_Slack_Table begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
|
|
||||||
</li>
|
|
||||||
<!--Setup_Slack_Table end-->
|
|
||||||
<!--Hold_Slack_Table begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
|
|
||||||
</li>
|
|
||||||
<!--Hold_Slack_Table end-->
|
|
||||||
<!--Recovery_Slack_Table begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
|
|
||||||
</li>
|
|
||||||
<!--Recovery_Slack_Table end-->
|
|
||||||
<!--Removal_Slack_Table begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
|
|
||||||
</li>
|
|
||||||
<!--Removal_Slack_Table end-->
|
|
||||||
</ul>
|
|
||||||
</li><!--All_Path_Slack_Table end-->
|
|
||||||
<!--MIN_PULSE_WIDTH_TABLE begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
|
|
||||||
</li>
|
|
||||||
<!--MIN_PULSE_WIDTH_TABLE end-->
|
|
||||||
<!--Timing_Report_by_Analysis_Type begin-->
|
|
||||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
|
|
||||||
<ul>
|
|
||||||
<!--Setup_Analysis begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Setup_Analysis end-->
|
|
||||||
<!--Hold_Analysis begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Hold_Analysis end-->
|
|
||||||
<!--Recovery_Analysis begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Recovery_Analysis end-->
|
|
||||||
<!--Removal_Analysis begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Removal_Analysis end-->
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
<!--Timing_Report_by_Analysis_Type end-->
|
|
||||||
<!--Minimum_Pulse_Width_Report begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Minimum_Pulse_Width_Report end-->
|
|
||||||
<!--High_Fanout_Nets_Report begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
|
|
||||||
<!--High_Fanout_Nets_Report end-->
|
|
||||||
<!--Route_Congestions_Report begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
|
|
||||||
<!--Route_Congestions_Report end-->
|
|
||||||
<!--Timing_Exceptions_Report begin-->
|
|
||||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
|
|
||||||
<ul>
|
|
||||||
<!--Setup_Analysis_Exceptions begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Setup_Analysis_Exceptions end-->
|
|
||||||
<!--Hold_Analysis_Exceptions begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Hold_Analysis_Exceptions end-->
|
|
||||||
<!--Recovery_Analysis_Exceptions begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Recovery_Analysis_Exceptions end-->
|
|
||||||
<!--Removal_Analysis_Exceptions begin-->
|
|
||||||
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="bttn_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
|
||||||
</li>
|
|
||||||
<!--Removal_Analysis_Exceptions end-->
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
<!--Timing_Exceptions_Report end-->
|
|
||||||
<!--SDC_Report begin-->
|
|
||||||
<li><div class="triangle_fake"></div><a href="bttn_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
|
|
||||||
<!--SDC_Report end-->
|
|
||||||
</ul>
|
|
||||||
</li>
|
|
||||||
<!-- details end-->
|
|
||||||
</ul>
|
|
||||||
</div><!-- catalog -->
|
|
||||||
</div><!-- catalog_wrapper -->
|
|
||||||
</body>
|
|
||||||
</html>
|
|
@ -1,257 +0,0 @@
|
|||||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
|
||||||
<html>
|
|
||||||
<head>
|
|
||||||
<title>Timing Analysis Report</title>
|
|
||||||
<style type="text/css">
|
|
||||||
@import url(../temp/style.css);
|
|
||||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
|
||||||
div#content { width: 100%; margin: }
|
|
||||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
|
||||||
h1, h3 { text-align: center; }
|
|
||||||
h1 {margin-top: 50px; }
|
|
||||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
|
||||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
|
||||||
th, td { padding: 5px 5px 5px 5px; }
|
|
||||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
|
||||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
|
||||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
|
||||||
</style>
|
|
||||||
</head>
|
|
||||||
<body>
|
|
||||||
<div id="content">
|
|
||||||
<h1><a name="Message">Timing Messages</a></h1>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Report Title</td>
|
|
||||||
<td>Timing Analysis Report</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Design File</td>
|
|
||||||
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Physical Constraints File</td>
|
|
||||||
<td>\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Timing Constraint File</td>
|
|
||||||
<td>---</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Tool Version</td>
|
|
||||||
<td>V1.9.9.03 Education (64-bit)</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Part Number</td>
|
|
||||||
<td>GW2A-LV18PG256C8/I7</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Device</td>
|
|
||||||
<td>GW2A-18</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Device Version</td>
|
|
||||||
<td>C</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Created Time</td>
|
|
||||||
<td>Mon Jan 20 17:48:16 2025
|
|
||||||
</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Legal Announcement</td>
|
|
||||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h1><a name="Summary">Timing Summaries</a></h1>
|
|
||||||
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
|
|
||||||
<table class="summary_table">
|
|
||||||
<tr>
|
|
||||||
<td class="label">Setup Delay Model</td>
|
|
||||||
<td>Slow 0.95V 85C C8/I7</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Hold Delay Model</td>
|
|
||||||
<td>Fast 1.05V 0C C8/I7</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Numbers of Paths Analyzed</td>
|
|
||||||
<td>158</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Numbers of Endpoints Analyzed</td>
|
|
||||||
<td>14</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Numbers of Falling Endpoints</td>
|
|
||||||
<td>0</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Numbers of Setup Violated Endpoints</td>
|
|
||||||
<td>0</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td class="label">Numbers of Hold Violated Endpoints</td>
|
|
||||||
<td>0</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Clock_Report">Clock Summary:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Clock Name</th>
|
|
||||||
<th class="label">Type</th>
|
|
||||||
<th class="label">Period</th>
|
|
||||||
<th class="label">Frequency(MHz)</th>
|
|
||||||
<th class="label">Rise</th>
|
|
||||||
<th class="label">Fall</th>
|
|
||||||
<th class="label">Source</th>
|
|
||||||
<th class="label">Master</th>
|
|
||||||
<th class="label">Objects</th>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
|
|
||||||
<table>
|
|
||||||
<tr>
|
|
||||||
<th>NO.</th>
|
|
||||||
<th>Clock Name</th>
|
|
||||||
<th>Constraint</th>
|
|
||||||
<th>Actual Fmax</th>
|
|
||||||
<th>Logic Level</th>
|
|
||||||
<th>Entity</th>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Clock Name</th>
|
|
||||||
<th class="label">Analysis Type</th>
|
|
||||||
<th class="label">Endpoints TNS</th>
|
|
||||||
<th class="label">Number of Endpoints</th>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h1><a name="Detail">Timing Details</a></h1>
|
|
||||||
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
|
|
||||||
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
|
|
||||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>Nothing to report!</h4>
|
|
||||||
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
|
||||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>Nothing to report!</h4>
|
|
||||||
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
|
||||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>Nothing to report!</h4>
|
|
||||||
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
|
||||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>Nothing to report!</h4>
|
|
||||||
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">Number</th>
|
|
||||||
<th class="label">Slack</th>
|
|
||||||
<th class="label">Actual Width</th>
|
|
||||||
<th class="label">Required Width</th>
|
|
||||||
<th class="label">Type</th>
|
|
||||||
<th class="label">Clock</th>
|
|
||||||
<th class="label">Objects</th>
|
|
||||||
</tr>
|
|
||||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
||||||
<h4>Nothing to report!</h4>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
|
||||||
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>No setup paths to report!</h4>
|
|
||||||
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>No hold paths to report!</h4>
|
|
||||||
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>No recovery paths to report!</h4>
|
|
||||||
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
||||||
<h4>No removal paths to report!</h4>
|
|
||||||
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
|
||||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
||||||
<h4>Nothing to report!</h4>
|
|
||||||
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
|
||||||
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">FANOUT</th>
|
|
||||||
<th class="label">NET NAME</th>
|
|
||||||
<th class="label">WORST SLACK</th>
|
|
||||||
<th class="label">MAX DELAY</th>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
|
||||||
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">GRID LOC</th>
|
|
||||||
<th class="label">ROUTE CONGESTIONS</th>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R27C30</td>
|
|
||||||
<td>43.06%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R29C29</td>
|
|
||||||
<td>43.06%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R27C29</td>
|
|
||||||
<td>40.28%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R26C29</td>
|
|
||||||
<td>33.33%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R26C30</td>
|
|
||||||
<td>31.94%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R29C28</td>
|
|
||||||
<td>30.56%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R29C30</td>
|
|
||||||
<td>29.17%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R27C28</td>
|
|
||||||
<td>26.39%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R27C31</td>
|
|
||||||
<td>25.00%</td>
|
|
||||||
</tr>
|
|
||||||
<tr>
|
|
||||||
<td>R26C28</td>
|
|
||||||
<td>25.00%</td>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
|
||||||
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
|
||||||
<h4>No timing exceptions to report!</h4>
|
|
||||||
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
|
||||||
<h4>No timing exceptions to report!</h4>
|
|
||||||
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
|
||||||
<h4>No timing exceptions to report!</h4>
|
|
||||||
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
|
||||||
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
|
||||||
<h4>No timing exceptions to report!</h4>
|
|
||||||
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
|
||||||
<table class="detail_table">
|
|
||||||
<tr>
|
|
||||||
<th class="label">SDC Command Type</th>
|
|
||||||
<th class="label">State</th>
|
|
||||||
<th class="label">Detail Command</th>
|
|
||||||
</tr>
|
|
||||||
</table>
|
|
||||||
</div><!-- content -->
|
|
||||||
</body>
|
|
||||||
</html>
|
|
@ -1,13 +0,0 @@
|
|||||||
-d \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\gwsynthesis\bttn.vg
|
|
||||||
-p GW2A-18C-PBGA256-8
|
|
||||||
-pn GW2A-LV18PG256C8/I7
|
|
||||||
-cst \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\src\bttn.cst
|
|
||||||
-cfg \\wsl.localhost\Debian\home\koray\code\verilog\gowin\bttn\impl\pnr\device.cfg
|
|
||||||
-bit
|
|
||||||
-tr
|
|
||||||
-ph
|
|
||||||
-timing
|
|
||||||
-cst_error
|
|
||||||
-correct_hold 1
|
|
||||||
-route_maxfan 23
|
|
||||||
-global_freq 100.000
|
|
@ -1,21 +0,0 @@
|
|||||||
set JTAG regular_io = false
|
|
||||||
set SSPI regular_io = false
|
|
||||||
set MSPI regular_io = false
|
|
||||||
set READY regular_io = false
|
|
||||||
set DONE regular_io = false
|
|
||||||
set I2C regular_io = false
|
|
||||||
set RECONFIG_N regular_io = false
|
|
||||||
set CRC_check = true
|
|
||||||
set compress = false
|
|
||||||
set encryption = false
|
|
||||||
set security_bit_enable = true
|
|
||||||
set bsram_init_fuse_print = true
|
|
||||||
set background_programming = off
|
|
||||||
set secure_mode = false
|
|
||||||
set program_done_bypass = false
|
|
||||||
set wake_up = 0
|
|
||||||
set format = binary
|
|
||||||
set power_on_reset_monitor = true
|
|
||||||
set multiboot_spi_flash_address = 0x00000000
|
|
||||||
set vccx = 3.3
|
|
||||||
set unused_pin = default
|
|
@ -1,143 +1,148 @@
|
|||||||
[
|
[
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
"InstLine" : 1,
|
"InstLine" : 1,
|
||||||
"InstName" : "bttn",
|
"InstName" : "bttn",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "bttn",
|
"ModuleName" : "bttn",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
|
<<<<<<< HEAD
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
"InstLine" : 11,
|
"InstLine" : 11,
|
||||||
|
=======
|
||||||
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
|
"InstLine" : 10,
|
||||||
|
>>>>>>> 15916a2c534beff06a16239dd4912b40b7f837b6
|
||||||
"InstName" : "a1",
|
"InstName" : "a1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "ALU",
|
"ModuleName" : "ALU",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"InstLine" : 18,
|
"InstLine" : 18,
|
||||||
"InstName" : "opCd",
|
"InstName" : "opCd",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "opCode"
|
"ModuleName" : "opCode"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"InstLine" : 20,
|
"InstLine" : 20,
|
||||||
"InstName" : "aU",
|
"InstName" : "aU",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "arithmeticUnit",
|
"ModuleName" : "arithmeticUnit",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
||||||
"InstLine" : 13,
|
"InstLine" : 13,
|
||||||
"InstName" : "a1",
|
"InstName" : "a1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "addition",
|
"ModuleName" : "addition",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 11,
|
"InstLine" : 11,
|
||||||
"InstName" : "f0",
|
"InstName" : "f0",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 12,
|
"InstLine" : 12,
|
||||||
"InstName" : "f1",
|
"InstName" : "f1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 13,
|
"InstLine" : 13,
|
||||||
"InstName" : "f2",
|
"InstName" : "f2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "f3",
|
"InstName" : "f3",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
@ -146,112 +151,112 @@
|
|||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "s1",
|
"InstName" : "s1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "subtraction",
|
"ModuleName" : "subtraction",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
|
||||||
"InstLine" : 11,
|
"InstLine" : 11,
|
||||||
"InstName" : "f0",
|
"InstName" : "f0",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fullsubtraction",
|
"ModuleName" : "fullsubtraction",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "hf1",
|
"InstName" : "hf1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "hf2",
|
"InstName" : "hf2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
|
||||||
"InstLine" : 12,
|
"InstLine" : 12,
|
||||||
"InstName" : "f1",
|
"InstName" : "f1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fullsubtraction",
|
"ModuleName" : "fullsubtraction",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "hf1",
|
"InstName" : "hf1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "hf2",
|
"InstName" : "hf2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
|
||||||
"InstLine" : 13,
|
"InstLine" : 13,
|
||||||
"InstName" : "f2",
|
"InstName" : "f2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fullsubtraction",
|
"ModuleName" : "fullsubtraction",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "hf1",
|
"InstName" : "hf1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "hf2",
|
"InstName" : "hf2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "f3",
|
"InstName" : "f3",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fullsubtraction",
|
"ModuleName" : "fullsubtraction",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "hf1",
|
"InstName" : "hf1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "hf2",
|
"InstName" : "hf2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfsubtraction"
|
"ModuleName" : "halfsubtraction"
|
||||||
}
|
}
|
||||||
@ -262,128 +267,128 @@
|
|||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"InstLine" : 21,
|
"InstLine" : 21,
|
||||||
"InstName" : "lU",
|
"InstName" : "lU",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "logicUnit"
|
"ModuleName" : "logicUnit"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"InstLine" : 22,
|
"InstLine" : 22,
|
||||||
"InstName" : "mU",
|
"InstName" : "mU",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "multiplier",
|
"ModuleName" : "multiplier",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
|
||||||
"InstLine" : 26,
|
"InstLine" : 26,
|
||||||
"InstName" : "add0",
|
"InstName" : "add0",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "addition",
|
"ModuleName" : "addition",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 11,
|
"InstLine" : 11,
|
||||||
"InstName" : "f0",
|
"InstName" : "f0",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 12,
|
"InstLine" : 12,
|
||||||
"InstName" : "f1",
|
"InstName" : "f1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 13,
|
"InstLine" : 13,
|
||||||
"InstName" : "f2",
|
"InstName" : "f2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "f3",
|
"InstName" : "f3",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
@ -392,112 +397,112 @@
|
|||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
|
||||||
"InstLine" : 42,
|
"InstLine" : 42,
|
||||||
"InstName" : "add1",
|
"InstName" : "add1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "addition",
|
"ModuleName" : "addition",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 11,
|
"InstLine" : 11,
|
||||||
"InstName" : "f0",
|
"InstName" : "f0",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 12,
|
"InstLine" : 12,
|
||||||
"InstName" : "f1",
|
"InstName" : "f1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 13,
|
"InstLine" : 13,
|
||||||
"InstName" : "f2",
|
"InstName" : "f2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "f3",
|
"InstName" : "f3",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
@ -506,112 +511,112 @@
|
|||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
|
||||||
"InstLine" : 58,
|
"InstLine" : 58,
|
||||||
"InstName" : "add2",
|
"InstName" : "add2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "addition",
|
"ModuleName" : "addition",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 11,
|
"InstLine" : 11,
|
||||||
"InstName" : "f0",
|
"InstName" : "f0",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 12,
|
"InstLine" : 12,
|
||||||
"InstName" : "f1",
|
"InstName" : "f1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 13,
|
"InstLine" : 13,
|
||||||
"InstName" : "f2",
|
"InstName" : "f2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "f3",
|
"InstName" : "f3",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "fulladder",
|
"ModuleName" : "fulladder",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 8,
|
"InstLine" : 8,
|
||||||
"InstName" : "h1",
|
"InstName" : "h1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"InstLine" : 9,
|
"InstLine" : 9,
|
||||||
"InstName" : "h2",
|
"InstName" : "h2",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "halfadder"
|
"ModuleName" : "halfadder"
|
||||||
}
|
}
|
||||||
@ -622,66 +627,66 @@
|
|||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"InstLine" : 76,
|
"InstLine" : 76,
|
||||||
"InstName" : "btod1",
|
"InstName" : "btod1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "BinaryToBCD",
|
"ModuleName" : "BinaryToBCD",
|
||||||
"SubInsts" : [
|
"SubInsts" : [
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 14,
|
"InstLine" : 14,
|
||||||
"InstName" : "d1t",
|
"InstName" : "d1t",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 23,
|
"InstLine" : 23,
|
||||||
"InstName" : "d2u",
|
"InstName" : "d2u",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 32,
|
"InstLine" : 32,
|
||||||
"InstName" : "d3v",
|
"InstName" : "d3v",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 41,
|
"InstLine" : 41,
|
||||||
"InstName" : "d4w",
|
"InstName" : "d4w",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 50,
|
"InstLine" : 50,
|
||||||
"InstName" : "d5x",
|
"InstName" : "d5x",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 59,
|
"InstLine" : 59,
|
||||||
"InstName" : "d6y",
|
"InstName" : "d6y",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"InstLine" : 68,
|
"InstLine" : 68,
|
||||||
"InstName" : "d7z",
|
"InstName" : "d7z",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "dabble"
|
"ModuleName" : "dabble"
|
||||||
}
|
}
|
||||||
@ -690,10 +695,15 @@
|
|||||||
]
|
]
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
|
<<<<<<< HEAD
|
||||||
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
"InstFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
"InstLine" : 12,
|
"InstLine" : 12,
|
||||||
|
=======
|
||||||
|
"InstFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
|
"InstLine" : 11,
|
||||||
|
>>>>>>> 15916a2c534beff06a16239dd4912b40b7f837b6
|
||||||
"InstName" : "s1",
|
"InstName" : "s1",
|
||||||
"ModuleFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
|
"ModuleFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
|
||||||
"ModuleLine" : 1,
|
"ModuleLine" : 1,
|
||||||
"ModuleName" : "selector"
|
"ModuleName" : "selector"
|
||||||
}
|
}
|
||||||
|
@ -2,63 +2,63 @@
|
|||||||
"Device" : "GW2A-18C",
|
"Device" : "GW2A-18C",
|
||||||
"Files" : [
|
"Files" : [
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/ALU.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/ALU.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/BinaryToBCD.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/addition.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/addition.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/arithmeticUnit.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/bttn.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/bttn.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/dabble.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/dabble.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fulladder.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fulladder.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/fullsubtraction.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfadder.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfadder.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/halfsubtraction.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/logicUnit.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/logicUnit.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/multiplier.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/multiplier.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/opCode.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/opCode.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/selector.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/selector.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/src/subtraction.v",
|
"Path" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/src/subtraction.v",
|
||||||
"Type" : "verilog"
|
"Type" : "verilog"
|
||||||
}
|
}
|
||||||
],
|
],
|
||||||
@ -66,7 +66,7 @@
|
|||||||
|
|
||||||
],
|
],
|
||||||
"LoopLimit" : 2000,
|
"LoopLimit" : 2000,
|
||||||
"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
|
"ResultFile" : "//wsl.localhost/Debian/home/akoray/code/verilog/gowin/bttn/impl/temp/rtl_parser.result",
|
||||||
"Top" : "",
|
"Top" : "",
|
||||||
"VerilogStd" : "verilog_2001",
|
"VerilogStd" : "verilog_2001",
|
||||||
"VhdlStd" : "vhdl_93"
|
"VhdlStd" : "vhdl_93"
|
||||||
|
2191
gowin/bttn/src/bttn
2191
gowin/bttn/src/bttn
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,23 +0,0 @@
|
|||||||
module bttnTB();
|
|
||||||
|
|
||||||
reg [3:0] A,B;
|
|
||||||
reg [2:0] opCodeA;
|
|
||||||
reg [1:0] select;
|
|
||||||
wire [11:0] Y;
|
|
||||||
|
|
||||||
bttn uut (
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.opCodeA(opCodeA),
|
|
||||||
.select(select),
|
|
||||||
.Y(Y)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("bttn.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
A = 4'b0001; B = 4'b0110; opCodeA = 3'b000; select = 2'b01; #5;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
2109
spartanTest/ALU
2109
spartanTest/ALU
File diff suppressed because it is too large
Load Diff
@ -1,79 +0,0 @@
|
|||||||
module ALU (
|
|
||||||
input [3:0] A, B,
|
|
||||||
input CarryIN,
|
|
||||||
input [2:0] opCodeA,
|
|
||||||
output [11:0] bcd,
|
|
||||||
output CarryOUT, overflow
|
|
||||||
);
|
|
||||||
|
|
||||||
// Supports: ADD[0], SUB[1], MULT[2], AND[4], OR[5], XOR[6]
|
|
||||||
|
|
||||||
wire [7:0] opCode8;
|
|
||||||
wire [3:0] add_Y, sub_Y;
|
|
||||||
wire [3:0] resultA, resultO, resultX, lUOutput1;
|
|
||||||
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
|
|
||||||
wire [3:0] wireY, wireLA;
|
|
||||||
wire [7:0] opwireM, wireM, Y;
|
|
||||||
|
|
||||||
opCode opCd (.A(opCodeA), .opCode(opCode8));
|
|
||||||
|
|
||||||
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
|
|
||||||
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
|
|
||||||
multiplier mU (.A(A), .B(B), .Y(opwireM));
|
|
||||||
|
|
||||||
or o01 (lUOutput1[0], resultA[0], resultO[0]);
|
|
||||||
or o02 (lUOutput1[1], resultA[1], resultO[1]);
|
|
||||||
or o03 (lUOutput1[2], resultA[2], resultO[2]);
|
|
||||||
or o04 (lUOutput1[3], resultA[3], resultO[3]);
|
|
||||||
|
|
||||||
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
|
|
||||||
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
|
|
||||||
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
|
|
||||||
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
|
|
||||||
|
|
||||||
|
|
||||||
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
|
|
||||||
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
|
|
||||||
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
|
|
||||||
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
|
|
||||||
|
|
||||||
|
|
||||||
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
|
|
||||||
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
|
|
||||||
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
|
|
||||||
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
|
|
||||||
|
|
||||||
and a21 (wireM[0], opCode8[2], opwireM[0]);
|
|
||||||
and a22 (wireM[1], opCode8[2], opwireM[1]);
|
|
||||||
and a23 (wireM[2], opCode8[2], opwireM[2]);
|
|
||||||
and a24 (wireM[3], opCode8[2], opwireM[3]);
|
|
||||||
and a25 (wireM[4], opCode8[2], opwireM[4]);
|
|
||||||
and a26 (wireM[5], opCode8[2], opwireM[5]);
|
|
||||||
and a27 (wireM[6], opCode8[2], opwireM[6]);
|
|
||||||
and a28 (wireM[7], opCode8[2], opwireM[7]);
|
|
||||||
|
|
||||||
|
|
||||||
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
|
|
||||||
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
|
|
||||||
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
|
|
||||||
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
|
|
||||||
|
|
||||||
|
|
||||||
or o1 (wireLA[0], lUOutput2[0], wireY[0]);
|
|
||||||
or o2 (wireLA[1], lUOutput2[1], wireY[1]);
|
|
||||||
or o3 (wireLA[2], lUOutput2[2], wireY[2]);
|
|
||||||
or o4 (wireLA[3], lUOutput2[3], wireY[3]);
|
|
||||||
|
|
||||||
or o31 (Y[0], wireLA[0], wireM[0]);
|
|
||||||
or o32 (Y[1], wireLA[1], wireM[1]);
|
|
||||||
or o33 (Y[2], wireLA[2], wireM[2]);
|
|
||||||
or o34 (Y[3], wireLA[3], wireM[3]);
|
|
||||||
or o35 (Y[4], 1'b0, wireM[4]);
|
|
||||||
or o36 (Y[5], 1'b0, wireM[5]);
|
|
||||||
or o37 (Y[6], 1'b0, wireM[6]);
|
|
||||||
or o38 (Y[7], 1'b0, wireM[7]);
|
|
||||||
|
|
||||||
BinaryToBCD btod1(.binary(Y), .bcd(bcd)); // WIRE Y BINARY!!!!
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
1074
spartanTest/ALU.vcd
1074
spartanTest/ALU.vcd
File diff suppressed because it is too large
Load Diff
@ -1,42 +0,0 @@
|
|||||||
module ALUTB ();
|
|
||||||
|
|
||||||
reg [3:0] A, B;
|
|
||||||
reg CarryIN;
|
|
||||||
reg [2:0] opCodeA;
|
|
||||||
wire CarryOUT, overflow;
|
|
||||||
wire [11:0] bcd;
|
|
||||||
|
|
||||||
ALU uut(
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.CarryIN(CarryIN),
|
|
||||||
.opCodeA(opCodeA),
|
|
||||||
.CarryOUT(CarryOUT),
|
|
||||||
.bcd(bcd),
|
|
||||||
.overflow(overflow)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
|
|
||||||
$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
|
|
||||||
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
|
|
||||||
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b011; #5;
|
|
||||||
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b011; #5;
|
|
||||||
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
|
|
||||||
A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b011; #5;
|
|
||||||
|
|
||||||
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
|
|
||||||
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b111; #5;
|
|
||||||
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b111; #5;
|
|
||||||
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
|
|
||||||
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b111; #5;
|
|
||||||
|
|
||||||
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
|
|
||||||
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b010; #5;
|
|
||||||
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b010; #5;
|
|
||||||
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
|
|
||||||
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b010; #5;
|
|
||||||
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,26 +0,0 @@
|
|||||||
module ALUtb ();
|
|
||||||
|
|
||||||
reg [3:0] A, B;
|
|
||||||
reg CarryIN;
|
|
||||||
reg [2:0] opCodeA;
|
|
||||||
wire [11:0] bcd;
|
|
||||||
wire CarryOUT, overflow;
|
|
||||||
|
|
||||||
ALU uut (
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.CarryIN(CarryIN),
|
|
||||||
.opCodeA(opCodeA),
|
|
||||||
.bcd(bcd),
|
|
||||||
.CarryOUT(CarryOUT),
|
|
||||||
.overflow(overflow)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("ALU.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
A = 4'b1100; B = 4'b1100; CarryIN = 1'b0; opCodeA = 3'b010; #5;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,79 +0,0 @@
|
|||||||
module BinaryToBCD (
|
|
||||||
input [7:0] binary,
|
|
||||||
output [11:0] bcd
|
|
||||||
);
|
|
||||||
|
|
||||||
wire empty1, empty2;
|
|
||||||
wire [3:0] dab1, dab2, dab3, dab4, dab5;
|
|
||||||
|
|
||||||
and a111 (empty1, 1'b0, 1'b0);
|
|
||||||
and a000 (empty2, 1'b0, 1'b0);
|
|
||||||
and a222 (bcd[11], 1'b0, 1'b0);
|
|
||||||
and a223 (bcd[10], 1'b0, 1'b0);
|
|
||||||
|
|
||||||
dabble d1t (.A((empty1)),
|
|
||||||
.B(binary[7]),
|
|
||||||
.C(binary[6]),
|
|
||||||
.D(binary[5]),
|
|
||||||
.X(dab1[0]),
|
|
||||||
.Y(dab1[1]),
|
|
||||||
.Z(dab1[2]),
|
|
||||||
.E(dab1[3]));
|
|
||||||
|
|
||||||
dabble d2u (.A((dab1[1])),
|
|
||||||
.B(dab1[2]),
|
|
||||||
.C(dab1[3]),
|
|
||||||
.D(binary[4]),
|
|
||||||
.X(dab2[0]),
|
|
||||||
.Y(dab2[1]),
|
|
||||||
.Z(dab2[2]),
|
|
||||||
.E(dab2[3]));
|
|
||||||
|
|
||||||
dabble d3v (.A((dab2[1])),
|
|
||||||
.B(dab2[2]),
|
|
||||||
.C(dab2[3]),
|
|
||||||
.D(binary[3]),
|
|
||||||
.X(dab3[0]),
|
|
||||||
.Y(dab3[1]),
|
|
||||||
.Z(dab3[2]),
|
|
||||||
.E(dab3[3]));
|
|
||||||
|
|
||||||
dabble d4w (.A((empty2)),
|
|
||||||
.B(dab1[0]),
|
|
||||||
.C(dab2[0]),
|
|
||||||
.D(dab3[0]),
|
|
||||||
.X(bcd[9]),
|
|
||||||
.Y(dab4[1]),
|
|
||||||
.Z(dab4[2]),
|
|
||||||
.E(dab4[3]));
|
|
||||||
|
|
||||||
dabble d5x (.A((dab3[1])),
|
|
||||||
.B(dab3[2]),
|
|
||||||
.C(dab3[3]),
|
|
||||||
.D(binary[2]),
|
|
||||||
.X(dab5[0]),
|
|
||||||
.Y(dab5[1]),
|
|
||||||
.Z(dab5[2]),
|
|
||||||
.E(dab5[3]));
|
|
||||||
|
|
||||||
dabble d6y (.A((dab4[1])),
|
|
||||||
.B(dab4[2]),
|
|
||||||
.C(dab4[3]),
|
|
||||||
.D(dab5[0]),
|
|
||||||
.X(bcd[8]),
|
|
||||||
.Y(bcd[7]),
|
|
||||||
.Z(bcd[6]),
|
|
||||||
.E(bcd[5]));
|
|
||||||
|
|
||||||
dabble d7z (.A((dab5[1])),
|
|
||||||
.B(dab5[2]),
|
|
||||||
.C(dab5[3]),
|
|
||||||
.D(binary[1]),
|
|
||||||
.X(bcd[4]),
|
|
||||||
.Y(bcd[3]),
|
|
||||||
.Z(bcd[2]),
|
|
||||||
.E(bcd[1]));
|
|
||||||
|
|
||||||
or o1 (bcd[0], binary[0], 1'b0);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,40 +0,0 @@
|
|||||||
module BinaryToBCDTB;
|
|
||||||
// Testbench signals
|
|
||||||
reg [7:0] binary;
|
|
||||||
wire [11:0] bcd; // Output BCD
|
|
||||||
|
|
||||||
// Instantiate the BinaryToBCD module
|
|
||||||
BinaryToBCD uut (
|
|
||||||
.binary(binary),
|
|
||||||
.bcd(bcd)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Testbench procedure
|
|
||||||
initial begin
|
|
||||||
$monitor("Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)",
|
|
||||||
$time, binary, bcd, bcd[11:8], bcd[7:4], bcd[3:0]);
|
|
||||||
$dumpfile("BinaryToBCD.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
// Test cases
|
|
||||||
binary = 8'b00000000; // Decimal: 0
|
|
||||||
#10;
|
|
||||||
|
|
||||||
binary = 8'b00001010; // Decimal: 10
|
|
||||||
#10;
|
|
||||||
|
|
||||||
binary = 8'b00101010; // Decimal: 42
|
|
||||||
#10;
|
|
||||||
|
|
||||||
binary = 8'b01100011; // Decimal: 99
|
|
||||||
#10;
|
|
||||||
|
|
||||||
binary = 8'b10011001; // Decimal: 153
|
|
||||||
#10;
|
|
||||||
|
|
||||||
binary = 8'b11111111; // Decimal: 255
|
|
||||||
#10;
|
|
||||||
|
|
||||||
// End simulation
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
endmodule
|
|
@ -1,20 +0,0 @@
|
|||||||
module addition (
|
|
||||||
input [3:0] A, B,
|
|
||||||
input CarryIN,
|
|
||||||
output [3:0] Y,
|
|
||||||
output CarryOUT,
|
|
||||||
output overflow
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [2:0] Carry4;
|
|
||||||
|
|
||||||
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
|
|
||||||
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
|
|
||||||
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
|
|
||||||
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
|
|
||||||
|
|
||||||
|
|
||||||
//overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow)); (KULLANILMAYACAK!!!!)
|
|
||||||
xor ov1 (overflow, Carry4[2], CarryOUT);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,33 +0,0 @@
|
|||||||
module arithmeticUnit (
|
|
||||||
input [1:0] opCode,
|
|
||||||
input [3:0] A, B,
|
|
||||||
input CarryIN,
|
|
||||||
output [3:0] add_Y, sub_Y,
|
|
||||||
output CarryOUT,
|
|
||||||
output overflow
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [3:0] addY, subY;
|
|
||||||
wire CarryOUTADD, CarryOUTSUB, tempCAdd, tempCSub, tempoverflow;
|
|
||||||
|
|
||||||
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(tempoverflow));
|
|
||||||
subtraction s1(.A(A), .B(B), .BorrowIN(CarryIN), .Y(subY), .BorrowOUT(CarryOUTSUB));
|
|
||||||
|
|
||||||
and add1 (add_Y[0], opCode[0], addY[0]);
|
|
||||||
and add2 (add_Y[1], opCode[0], addY[1]);
|
|
||||||
and add3 (add_Y[2], opCode[0], addY[2]);
|
|
||||||
and add4 (add_Y[3], opCode[0], addY[3]);
|
|
||||||
|
|
||||||
and sub1 (sub_Y[0], opCode[1], subY[0]);
|
|
||||||
and sub2 (sub_Y[1], opCode[1], subY[1]);
|
|
||||||
and sub3 (sub_Y[2], opCode[1], subY[2]);
|
|
||||||
and sub4 (sub_Y[3], opCode[1], subY[3]);
|
|
||||||
|
|
||||||
// or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB); (OLD!!!)
|
|
||||||
and and10 (tempCSub, CarryOUTSUB, opCode[1]);
|
|
||||||
and and11 (tempCAdd, CarryOUTADD, opCode[0]);
|
|
||||||
or or4 (CarryOUT, tempCAdd, tempCSub);
|
|
||||||
|
|
||||||
and add12 (overflow, opCode[0], tempoverflow);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,41 +0,0 @@
|
|||||||
module char_mem (
|
|
||||||
input [4:0] addr,
|
|
||||||
output [7:0] bus,
|
|
||||||
input [3:0] A,
|
|
||||||
input [3:0] B,
|
|
||||||
input [2:0] opCode,
|
|
||||||
input [7:0] Y
|
|
||||||
);
|
|
||||||
parameter LINES = 2;
|
|
||||||
parameter CHARS_PER_LINE = 16;
|
|
||||||
parameter BITS_PER_CHAR = 8;
|
|
||||||
parameter STR_SIZE = LINES * CHARS_PER_LINE * BITS_PER_CHAR;
|
|
||||||
|
|
||||||
// Map the data into strings for display
|
|
||||||
wire [127:0] line1 = { "A:", nibble_to_ascii(A), " B:", nibble_to_ascii(B), " " };
|
|
||||||
wire [127:0] line2 = { "op:", nibble_to_ascii({1'b0, opCode}), " Y:", byte_to_ascii(Y) };
|
|
||||||
|
|
||||||
// Combine the two lines
|
|
||||||
wire [0:STR_SIZE-1] display_data = { line1, line2 };
|
|
||||||
|
|
||||||
// Address selection for the LCD
|
|
||||||
assign bus = display_data[{addr[4:0], 3'b000}+:8];
|
|
||||||
|
|
||||||
// Converts a 4-bit nibble to two ASCII characters
|
|
||||||
function [15:0] nibble_to_ascii;
|
|
||||||
input [3:0] nibble;
|
|
||||||
begin
|
|
||||||
nibble_to_ascii[15:8] = (nibble[3:0] >= 4'd10) ? (nibble[3:0] - 4'd10 + "A") : (nibble[3:0] + "0");
|
|
||||||
nibble_to_ascii[7:0] = " ";
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
// Converts an 8-bit byte to two ASCII characters
|
|
||||||
function [15:0] byte_to_ascii;
|
|
||||||
input [7:0] byte;
|
|
||||||
begin
|
|
||||||
byte_to_ascii[15:8] = ((byte >> 4) >= 4'd10) ? ((byte >> 4) - 4'd10 + "A") : ((byte >> 4) + "0");
|
|
||||||
byte_to_ascii[7:0] = ((byte & 4'hF) >= 4'd10) ? ((byte & 4'hF) - 4'd10 + "A") : ((byte & 4'hF) + "0");
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
endmodule
|
|
@ -1,22 +0,0 @@
|
|||||||
module dabble (
|
|
||||||
input A, B, C, D,
|
|
||||||
output X, Y, Z, E
|
|
||||||
);
|
|
||||||
|
|
||||||
wire xor1, nor1, xor2, nor2, nor3, or1;
|
|
||||||
|
|
||||||
xor xo1 (xor1, A, D);
|
|
||||||
nor no1 (nor1, A, B);
|
|
||||||
xor xo2 (xor2, A, C);
|
|
||||||
|
|
||||||
nor no2 (nor2, xor1, xor2);
|
|
||||||
|
|
||||||
nor no3 (nor3, nor2, nor1);
|
|
||||||
buf bu1 (X, nor3);
|
|
||||||
or o1 (or1, xor1, nor1);
|
|
||||||
|
|
||||||
nor no4 (Y, or1, C);
|
|
||||||
and an1 (Z, or1, xor2);
|
|
||||||
xor xo3 (E, nor3, D);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,105 +0,0 @@
|
|||||||
JEDEC Programming File for /home/ise/ise/data.jed
|
|
||||||
Date: Sat Oct 26 08:09:00 2024
|
|
||||||
|
|
||||||
QF25812*
|
|
||||||
QP0*
|
|
||||||
F0*
|
|
||||||
X0*
|
|
||||||
N DEVICE xc2c64a-XXXXX*
|
|
||||||
L000000 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L000274 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L000548 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L000822 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L001096 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L001370 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L001644 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L001918 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L002192 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L002466 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L002740 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L003014 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L003288 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L003562 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L003836 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L004110 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L004384 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L004658 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L004932 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L005206 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L005480 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L005754 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111000001111001*
|
|
||||||
L006028 1111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111*
|
|
||||||
L006302 1001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110101101111111111111111111*
|
|
||||||
L006576 1111111111111111111111111111111111111110110101111111111111111111111111101101011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L006850 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L007124 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L007398 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L007672 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L007946 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L008220 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L008494 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L008768 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L009042 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L009316 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L009590 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L009864 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L010138 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L010412 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110111111101110111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L010686 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L010960 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L011234 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L011508 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L011782 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L012056 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L012330 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000111100111111001111110000000111100001110001111110000000111100111111001111110000000111100111111001111110000000111100111111001111110000000*
|
|
||||||
L012604 1111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111100110000001000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111*
|
|
||||||
L012878 0011111100111111001111111111111111111111111111111111111111111111111111111111111111111111101111010111111111111111111111111010110111111111111111111111001110111111111111111111111111111111101101011111111111111111111111111011010111111111111111111111111111111111111111111111111111*
|
|
||||||
L013152 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L013426 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L013700 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L013974 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111101110111111011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L014248 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L014522 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L014796 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L015070 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L015344 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110111011111101111011111111111111111111111111111111111111111111111111111111*
|
|
||||||
L015618 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L015892 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L016166 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L016440 1111111111111111111111111111111111111111111111111111111111111111111111110111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L016714 1111111111111111111111111111111111111101111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L016988 1111011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L017262 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L017536 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L017810 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L018084 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L018358 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L018632 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L018906 1111110000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011001001110001010000011110011111100111111000000011110011111100111111000000011110011111100111111000000011110011111010110001*
|
|
||||||
L019180 0100000111100111110101100010100000111100111110101100010100000111100111111001111110000000111100111110101100010100000111100111111001111110000000111100111111001111110011111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L019454 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L019728 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L020002 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L020276 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L020550 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L020824 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L021098 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L021372 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L021646 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L021920 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L022194 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L022468 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L022742 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L023016 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L023290 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L023564 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L023838 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L024112 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L024386 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L024660 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L024934 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111*
|
|
||||||
L025208 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100000111100001110001111110000000111100001110001111110000000111100111111001111110000000111100111111001111110000000111100111*
|
|
||||||
L025482 1110011111100000001111001111110011111100000001111000011100011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110011111100000001111001111110*
|
|
||||||
L025756 01111110000000111100111111001111110000000111111110111111*
|
|
||||||
C2A9A*
|
|
||||||
0296
|
|
@ -1,12 +0,0 @@
|
|||||||
module fulladder (
|
|
||||||
input A, B, Carry,
|
|
||||||
output Sum, CarryO
|
|
||||||
);
|
|
||||||
|
|
||||||
wire xor1, and1, and2;
|
|
||||||
|
|
||||||
halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
|
|
||||||
halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
|
|
||||||
or o1 (CarryO, and1, and2);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,12 +0,0 @@
|
|||||||
module fullsubtraction (
|
|
||||||
input A, B, BorrowIN,
|
|
||||||
output Difference, BorrowOut
|
|
||||||
);
|
|
||||||
|
|
||||||
wire tempD, tempB1, tempB2;
|
|
||||||
|
|
||||||
halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
|
|
||||||
halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
|
|
||||||
or o1 (BorrowOut, tempB1, tempB2);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,9 +0,0 @@
|
|||||||
module halfadder (
|
|
||||||
input A, B,
|
|
||||||
output Sum, Carry
|
|
||||||
);
|
|
||||||
|
|
||||||
and a1 (Carry, A, B);
|
|
||||||
xor xo1 (Sum, A, B);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,12 +0,0 @@
|
|||||||
module halfsubtraction (
|
|
||||||
input A, B,
|
|
||||||
output Difference, Borrow
|
|
||||||
);
|
|
||||||
|
|
||||||
wire notA;
|
|
||||||
|
|
||||||
xor xo1 (Difference, A, B);
|
|
||||||
not a1 (notA, A);
|
|
||||||
and an1 (Borrow, notA, B);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,53 +0,0 @@
|
|||||||
module lcd (
|
|
||||||
input clk,
|
|
||||||
output reg lcd_rs,
|
|
||||||
output reg lcd_rw,
|
|
||||||
output reg lcd_e,
|
|
||||||
output reg [7:4] lcd_d,
|
|
||||||
output [4:0] mem_addr,
|
|
||||||
input [7:0] mem_bus
|
|
||||||
);
|
|
||||||
|
|
||||||
parameter n = 24;
|
|
||||||
parameter j = 17; // Initialization is slow, runs at clk/2^(j+2) ~95Hz
|
|
||||||
parameter k = 11; // Writing/seeking is fast, clk/2^(k_2) ~6KHz
|
|
||||||
parameter noop = 6'b010000; // Allows LCD to drive lcd_d, can be safely written any time
|
|
||||||
|
|
||||||
reg [n:0] count = 0;
|
|
||||||
reg [5:0] lcd_state = noop;
|
|
||||||
reg init = 1; // Start in initialization on power on
|
|
||||||
reg row = 0; // Writing to top or or bottom row
|
|
||||||
|
|
||||||
assign mem_addr = {row, count[k+6:k+3]};
|
|
||||||
|
|
||||||
initial count[j+7:j+2] = 11;
|
|
||||||
|
|
||||||
always @ (posedge clk) begin
|
|
||||||
count <= count + 1;
|
|
||||||
if (init) begin // initalization
|
|
||||||
case (count[j+7:j+2])
|
|
||||||
1: lcd_state <= 6'b000010; // function set
|
|
||||||
2: lcd_state <= 6'b000010;
|
|
||||||
3: lcd_state <= 6'b001000;
|
|
||||||
4: lcd_state <= 6'b000000; // display on/off control
|
|
||||||
5: lcd_state <= 6'b001100;
|
|
||||||
6: lcd_state <= 6'b000000; // display clear
|
|
||||||
7: lcd_state <= 6'b000001;
|
|
||||||
8: lcd_state <= 6'b000000; // entry mode set
|
|
||||||
9: lcd_state <= 6'b000110;
|
|
||||||
10: begin init <= ~init; count <= 0; end
|
|
||||||
endcase
|
|
||||||
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
|
|
||||||
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[j+1:j+0] & ~lcd_rw,lcd_state};
|
|
||||||
end else begin // Continuously update screen from memory
|
|
||||||
case (count[k+7:k+2])
|
|
||||||
32: lcd_state <= {3'b001,~row,2'b00}; // Move cursor to begining of next line
|
|
||||||
33: lcd_state <= 6'b000000;
|
|
||||||
34: begin count <= 0; row <= ~row; end // Restart and switch which row is being written
|
|
||||||
default: lcd_state <= {2'b10, ~count[k+2] ? mem_bus[7:4] : mem_bus[3:0]}; // Pull characters from bus
|
|
||||||
endcase
|
|
||||||
// Write lcd_state to the LCD and turn lcd_e high for the middle half of each lcd_state
|
|
||||||
{lcd_e,lcd_rs,lcd_rw,lcd_d[7:4]} <= {^count[k+1:k+0] & ~lcd_rw,lcd_state};
|
|
||||||
end
|
|
||||||
end
|
|
||||||
endmodule
|
|
@ -1,39 +0,0 @@
|
|||||||
module logicUnit (
|
|
||||||
input [2:0] opCode,
|
|
||||||
input [3:0] A, B,
|
|
||||||
output [3:0] resultA, resultO, resultX
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [3:0] and1, or1, xor1;
|
|
||||||
|
|
||||||
and a01 (and1[0], A[0], B[0]);
|
|
||||||
and a02 (and1[1], A[1], B[1]);
|
|
||||||
and a03 (and1[2], A[2], B[2]);
|
|
||||||
and a04 (and1[3], A[3], B[3]);
|
|
||||||
|
|
||||||
or o01 (or1[0], A[0], B[0]);
|
|
||||||
or o02 (or1[1], A[1], B[1]);
|
|
||||||
or o03 (or1[2], A[2], B[2]);
|
|
||||||
or o04 (or1[3], A[3], B[3]);
|
|
||||||
|
|
||||||
xor xor01 (xor1[0], A[0], B[0]);
|
|
||||||
xor xor02 (xor1[1], A[1], B[1]);
|
|
||||||
xor xor03 (xor1[2], A[2], B[2]);
|
|
||||||
xor xor04 (xor1[3], A[3], B[3]);
|
|
||||||
|
|
||||||
and a_o1 (resultA[0], opCode[0], and1[0]);
|
|
||||||
and a_o2 (resultA[1], opCode[0], and1[1]);
|
|
||||||
and a_o3 (resultA[2], opCode[0], and1[2]);
|
|
||||||
and a_o4 (resultA[3], opCode[0], and1[3]);
|
|
||||||
|
|
||||||
and o_o1 (resultO[0], opCode[1], or1[0]);
|
|
||||||
and o_o2 (resultO[1], opCode[1], or1[1]);
|
|
||||||
and o_o3 (resultO[2], opCode[1], or1[2]);
|
|
||||||
and o_o4 (resultO[3], opCode[1], or1[3]);
|
|
||||||
|
|
||||||
and x_o1 (resultX[0], opCode[2], xor1[0]);
|
|
||||||
and x_o2 (resultX[1], opCode[2], xor1[1]);
|
|
||||||
and x_o3 (resultX[2], opCode[2], xor1[2]);
|
|
||||||
and x_o4 (resultX[3], opCode[2], xor1[3]);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,37 +0,0 @@
|
|||||||
module logicUnitTB ();
|
|
||||||
|
|
||||||
reg [2:0] opCode;
|
|
||||||
reg [3:0] A, B;
|
|
||||||
wire [3:0] resultA, resultO, resultX;
|
|
||||||
|
|
||||||
logicUnit uut (
|
|
||||||
.opCode(opCode),
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.resultA(resultA),
|
|
||||||
.resultO(resultO),
|
|
||||||
.resultX(resultX)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("logicUnit.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
opCode = 3'b001; A = 4'b0001; B = 4'b0001; #2;
|
|
||||||
opCode = 3'b001; A = 4'b0011; B = 4'b0001; #2;
|
|
||||||
opCode = 3'b001; A = 4'b1001; B = 4'b1001; #2;
|
|
||||||
opCode = 3'b001; A = 4'b1111; B = 4'b1111; #2;
|
|
||||||
opCode = 3'b001; A = 4'b0000; B = 4'b0000; #2;
|
|
||||||
|
|
||||||
opCode = 3'b010; A = 4'b0001; B = 4'b0101; #2;
|
|
||||||
opCode = 3'b010; A = 4'b1001; B = 4'b0101; #2;
|
|
||||||
opCode = 3'b010; A = 4'b0001; B = 4'b1111; #2;
|
|
||||||
opCode = 3'b010; A = 4'b0000; B = 4'b0101; #2;
|
|
||||||
|
|
||||||
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
|
|
||||||
opCode = 3'b100; A = 4'b0000; B = 4'b0000; #2;
|
|
||||||
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
|
|
||||||
opCode = 3'b100; A = 4'b1111; B = 4'b1111; #2;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,76 +0,0 @@
|
|||||||
module multiplier (
|
|
||||||
input [3:0] A, B,
|
|
||||||
output [7:0] Y
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [3:0] b0, a0, a1, a2;
|
|
||||||
wire [4:0] S0, S1, S2;
|
|
||||||
wire carry0, carry1, carry2;
|
|
||||||
wire overflow0, overflow1, overflow2;
|
|
||||||
|
|
||||||
// Partial product generation
|
|
||||||
and (Y[0], A[0], B[0]); // LSB of the result
|
|
||||||
|
|
||||||
// Generate partial products for B[0] and B[1]
|
|
||||||
and ab00 (b0[0], A[1], B[0]);
|
|
||||||
and ab01 (b0[1], A[2], B[0]);
|
|
||||||
and ab02 (b0[2], A[3], B[0]);
|
|
||||||
not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
|
|
||||||
|
|
||||||
and aa00 (a0[0], A[0], B[1]);
|
|
||||||
and aa01 (a0[1], A[1], B[1]);
|
|
||||||
and aa02 (a0[2], A[2], B[1]);
|
|
||||||
and aa03 (a0[3], A[3], B[1]);
|
|
||||||
|
|
||||||
// First addition
|
|
||||||
addition add0 (
|
|
||||||
.A(a0),
|
|
||||||
.B(b0),
|
|
||||||
.CarryIN(1'b0),
|
|
||||||
.Y(S0[3:0]),
|
|
||||||
.CarryOUT(S0[4]),
|
|
||||||
.overflow(overflow0)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Generate partial products for B[2]
|
|
||||||
and aa10 (a1[0], A[0], B[2]);
|
|
||||||
and aa11 (a1[1], A[1], B[2]);
|
|
||||||
and aa12 (a1[2], A[2], B[2]);
|
|
||||||
and aa13 (a1[3], A[3], B[2]);
|
|
||||||
|
|
||||||
// Second addition
|
|
||||||
addition add1 (
|
|
||||||
.A(a1),
|
|
||||||
.B(S0[4:1]),
|
|
||||||
.CarryIN(1'b0),
|
|
||||||
.Y(S1[3:0]),
|
|
||||||
.CarryOUT(S1[4]),
|
|
||||||
.overflow(overflow1)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Generate partial products for B[3]
|
|
||||||
and aa20 (a2[0], A[0], B[3]);
|
|
||||||
and aa21 (a2[1], A[1], B[3]);
|
|
||||||
and aa22 (a2[2], A[2], B[3]);
|
|
||||||
and aa23 (a2[3], A[3], B[3]);
|
|
||||||
|
|
||||||
// Third addition
|
|
||||||
addition add2 (
|
|
||||||
.A(a2),
|
|
||||||
.B(S1[4:1]),
|
|
||||||
.CarryIN(1'b0),
|
|
||||||
.Y(S2[3:0]),
|
|
||||||
.CarryOUT(S2[4]),
|
|
||||||
.overflow(overflow2)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Combine results into the final output Y
|
|
||||||
or o01 (Y[1], S0[0], 1'b0);
|
|
||||||
or o02 (Y[2], S1[0], 1'b0);
|
|
||||||
or o03 (Y[3], S2[0], 1'b0);
|
|
||||||
or o04 (Y[4], S2[1], 1'b0);
|
|
||||||
or o05 (Y[5], S2[2], 1'b0);
|
|
||||||
or o06 (Y[6], S2[3], 1'b0);
|
|
||||||
or o07 (Y[7], S2[4], 1'b0);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,22 +0,0 @@
|
|||||||
module multiplierTB();
|
|
||||||
reg [3:0] A, B;
|
|
||||||
wire [7:0] Y;
|
|
||||||
|
|
||||||
multiplier uut(
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.Y(Y)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("multiplier.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
A = 4'b0000; B = 4'b0000; #2;
|
|
||||||
A = 4'b0000; B = 4'b1000; #2;
|
|
||||||
A = 4'b1000; B = 4'b1000; #2;
|
|
||||||
A = 4'b0111; B = 4'b0111; #2;
|
|
||||||
A = 4'b1111; B = 4'b1111; #2;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,25 +0,0 @@
|
|||||||
module opCode (
|
|
||||||
input [2:0] A,
|
|
||||||
output [7:0] opCode
|
|
||||||
);
|
|
||||||
wire and1, and2, and3, and4, notA, notB, notC;
|
|
||||||
|
|
||||||
not n1(notA, A[2]);
|
|
||||||
not n2(notB, A[1]);
|
|
||||||
not n3(notC, A[0]);
|
|
||||||
|
|
||||||
and a01(and1, A[2], A[1]);
|
|
||||||
and a02(and2, notA, A[1]);
|
|
||||||
and a03(and3, A[2], notB);
|
|
||||||
and a04(and4, notA, notB);
|
|
||||||
|
|
||||||
and a1(opCode[0], and4, notC);
|
|
||||||
and a2(opCode[1], and4, A[0]);
|
|
||||||
and a3(opCode[2], and2, notC);
|
|
||||||
and a4(opCode[3], and2, A[0]);
|
|
||||||
and a5(opCode[4], and3, notC);
|
|
||||||
and a6(opCode[5], and3, A[0]);
|
|
||||||
and a7(opCode[6], and1, notC);
|
|
||||||
and a8(opCode[7], and1, A[0]);
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,26 +0,0 @@
|
|||||||
module opCodeTB();
|
|
||||||
|
|
||||||
reg [2:0] A;
|
|
||||||
wire [7:0] opCode;
|
|
||||||
|
|
||||||
opCode uut (
|
|
||||||
.A(A),
|
|
||||||
|
|
||||||
.opCode(opCode)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("opCode.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
A = 3'b000; #3;
|
|
||||||
A = 3'b001; #3;
|
|
||||||
A = 3'b010; #3;
|
|
||||||
A = 3'b011; #3;
|
|
||||||
A = 3'b100; #3;
|
|
||||||
A = 3'b101; #3;
|
|
||||||
A = 3'b110; #3;
|
|
||||||
A = 3'b111; #3;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,140 +0,0 @@
|
|||||||
#! /usr/bin/vvp
|
|
||||||
:ivl_version "11.0 (stable)";
|
|
||||||
:ivl_delay_selection "TYPICAL";
|
|
||||||
:vpi_time_precision + 0;
|
|
||||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
|
||||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
|
||||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
|
||||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
|
||||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
|
||||||
S_0x558eb92edb80 .scope module, "selectorTB" "selectorTB" 2 1;
|
|
||||||
.timescale 0 0;
|
|
||||||
v0x558eb9317af0_0 .var "A", 3 0;
|
|
||||||
v0x558eb9317bd0_0 .var "ALUY", 7 0;
|
|
||||||
v0x558eb9317ca0_0 .var "B", 3 0;
|
|
||||||
v0x558eb9317da0_0 .net "Y", 7 0, v0x558eb9317740_0; 1 drivers
|
|
||||||
v0x558eb9317e70_0 .var "opCodeA", 2 0;
|
|
||||||
v0x558eb9317f60_0 .var "select", 1 0;
|
|
||||||
S_0x558eb9302140 .scope module, "uut" "selector" 2 9, 3 1 0, S_0x558eb92edb80;
|
|
||||||
.timescale 0 0;
|
|
||||||
.port_info 0 /INPUT 4 "A";
|
|
||||||
.port_info 1 /INPUT 4 "B";
|
|
||||||
.port_info 2 /INPUT 3 "opCodeA";
|
|
||||||
.port_info 3 /INPUT 2 "select";
|
|
||||||
.port_info 4 /INPUT 8 "ALUY";
|
|
||||||
.port_info 5 /OUTPUT 8 "Y";
|
|
||||||
v0x558eb9302350_0 .net "A", 3 0, v0x558eb9317af0_0; 1 drivers
|
|
||||||
v0x558eb93175a0_0 .net "ALUY", 7 0, v0x558eb9317bd0_0; 1 drivers
|
|
||||||
v0x558eb9317680_0 .net "B", 3 0, v0x558eb9317ca0_0; 1 drivers
|
|
||||||
v0x558eb9317740_0 .var "Y", 7 0;
|
|
||||||
v0x558eb9317820_0 .net "opCodeA", 2 0, v0x558eb9317e70_0; 1 drivers
|
|
||||||
v0x558eb9317950_0 .net "select", 1 0, v0x558eb9317f60_0; 1 drivers
|
|
||||||
E_0x558eb93001f0/0 .event edge, v0x558eb9317950_0, v0x558eb9302350_0, v0x558eb9317680_0, v0x558eb9317820_0;
|
|
||||||
E_0x558eb93001f0/1 .event edge, v0x558eb93175a0_0;
|
|
||||||
E_0x558eb93001f0 .event/or E_0x558eb93001f0/0, E_0x558eb93001f0/1;
|
|
||||||
.scope S_0x558eb9302140;
|
|
||||||
T_0 ;
|
|
||||||
%wait E_0x558eb93001f0;
|
|
||||||
%load/vec4 v0x558eb9317950_0;
|
|
||||||
%dup/vec4;
|
|
||||||
%pushi/vec4 0, 0, 2;
|
|
||||||
%cmp/u;
|
|
||||||
%jmp/1 T_0.0, 6;
|
|
||||||
%dup/vec4;
|
|
||||||
%pushi/vec4 1, 0, 2;
|
|
||||||
%cmp/u;
|
|
||||||
%jmp/1 T_0.1, 6;
|
|
||||||
%dup/vec4;
|
|
||||||
%pushi/vec4 2, 0, 2;
|
|
||||||
%cmp/u;
|
|
||||||
%jmp/1 T_0.2, 6;
|
|
||||||
%dup/vec4;
|
|
||||||
%pushi/vec4 3, 0, 2;
|
|
||||||
%cmp/u;
|
|
||||||
%jmp/1 T_0.3, 6;
|
|
||||||
%pushi/vec4 0, 0, 8;
|
|
||||||
%store/vec4 v0x558eb9317740_0, 0, 8;
|
|
||||||
%jmp T_0.5;
|
|
||||||
T_0.0 ;
|
|
||||||
%pushi/vec4 0, 0, 4;
|
|
||||||
%load/vec4 v0x558eb9302350_0;
|
|
||||||
%concat/vec4; draw_concat_vec4
|
|
||||||
%store/vec4 v0x558eb9317740_0, 0, 8;
|
|
||||||
%jmp T_0.5;
|
|
||||||
T_0.1 ;
|
|
||||||
%pushi/vec4 0, 0, 4;
|
|
||||||
%load/vec4 v0x558eb9317680_0;
|
|
||||||
%concat/vec4; draw_concat_vec4
|
|
||||||
%store/vec4 v0x558eb9317740_0, 0, 8;
|
|
||||||
%jmp T_0.5;
|
|
||||||
T_0.2 ;
|
|
||||||
%pushi/vec4 0, 0, 5;
|
|
||||||
%load/vec4 v0x558eb9317820_0;
|
|
||||||
%concat/vec4; draw_concat_vec4
|
|
||||||
%store/vec4 v0x558eb9317740_0, 0, 8;
|
|
||||||
%jmp T_0.5;
|
|
||||||
T_0.3 ;
|
|
||||||
%load/vec4 v0x558eb93175a0_0;
|
|
||||||
%store/vec4 v0x558eb9317740_0, 0, 8;
|
|
||||||
%jmp T_0.5;
|
|
||||||
T_0.5 ;
|
|
||||||
%pop/vec4 1;
|
|
||||||
%jmp T_0;
|
|
||||||
.thread T_0, $push;
|
|
||||||
.scope S_0x558eb92edb80;
|
|
||||||
T_1 ;
|
|
||||||
%vpi_call 2 19 "$dumpfile", "selector.vcd" {0 0 0};
|
|
||||||
%vpi_call 2 20 "$dumpvars" {0 0 0};
|
|
||||||
%pushi/vec4 1, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317af0_0, 0, 4;
|
|
||||||
%pushi/vec4 2, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317ca0_0, 0, 4;
|
|
||||||
%pushi/vec4 7, 0, 3;
|
|
||||||
%store/vec4 v0x558eb9317e70_0, 0, 3;
|
|
||||||
%pushi/vec4 240, 0, 8;
|
|
||||||
%store/vec4 v0x558eb9317bd0_0, 0, 8;
|
|
||||||
%pushi/vec4 0, 0, 2;
|
|
||||||
%store/vec4 v0x558eb9317f60_0, 0, 2;
|
|
||||||
%delay 5, 0;
|
|
||||||
%pushi/vec4 1, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317af0_0, 0, 4;
|
|
||||||
%pushi/vec4 2, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317ca0_0, 0, 4;
|
|
||||||
%pushi/vec4 7, 0, 3;
|
|
||||||
%store/vec4 v0x558eb9317e70_0, 0, 3;
|
|
||||||
%pushi/vec4 240, 0, 8;
|
|
||||||
%store/vec4 v0x558eb9317bd0_0, 0, 8;
|
|
||||||
%pushi/vec4 1, 0, 2;
|
|
||||||
%store/vec4 v0x558eb9317f60_0, 0, 2;
|
|
||||||
%delay 5, 0;
|
|
||||||
%pushi/vec4 1, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317af0_0, 0, 4;
|
|
||||||
%pushi/vec4 2, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317ca0_0, 0, 4;
|
|
||||||
%pushi/vec4 7, 0, 3;
|
|
||||||
%store/vec4 v0x558eb9317e70_0, 0, 3;
|
|
||||||
%pushi/vec4 112, 0, 8;
|
|
||||||
%store/vec4 v0x558eb9317bd0_0, 0, 8;
|
|
||||||
%pushi/vec4 2, 0, 2;
|
|
||||||
%store/vec4 v0x558eb9317f60_0, 0, 2;
|
|
||||||
%delay 5, 0;
|
|
||||||
%pushi/vec4 1, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317af0_0, 0, 4;
|
|
||||||
%pushi/vec4 2, 0, 4;
|
|
||||||
%store/vec4 v0x558eb9317ca0_0, 0, 4;
|
|
||||||
%pushi/vec4 7, 0, 3;
|
|
||||||
%store/vec4 v0x558eb9317e70_0, 0, 3;
|
|
||||||
%pushi/vec4 112, 0, 8;
|
|
||||||
%store/vec4 v0x558eb9317bd0_0, 0, 8;
|
|
||||||
%pushi/vec4 3, 0, 2;
|
|
||||||
%store/vec4 v0x558eb9317f60_0, 0, 2;
|
|
||||||
%delay 5, 0;
|
|
||||||
%vpi_call 2 25 "$finish" {0 0 0};
|
|
||||||
%end;
|
|
||||||
.thread T_1;
|
|
||||||
# The file index is used to find the file name in the following table.
|
|
||||||
:file_names 4;
|
|
||||||
"N/A";
|
|
||||||
"<interactive>";
|
|
||||||
"selectorTB.v";
|
|
||||||
"selector.v";
|
|
@ -1,20 +0,0 @@
|
|||||||
module selector (
|
|
||||||
input [3:0] A,
|
|
||||||
input [3:0] B,
|
|
||||||
input [2:0] opCodeA,
|
|
||||||
input [1:0] select,
|
|
||||||
input [7:0] ALUY,
|
|
||||||
output reg [7:0] Y
|
|
||||||
);
|
|
||||||
|
|
||||||
always @(*) begin
|
|
||||||
case (select)
|
|
||||||
2'b00: Y = {4'b0000, A}; // Zero-extend A to 8 bits
|
|
||||||
2'b01: Y = {4'b0000, B}; // Zero-extend B to 8 bits
|
|
||||||
2'b10: Y = {5'b00000, opCodeA}; // Zero-extend opCodeA to 8 bits
|
|
||||||
2'b11: Y = ALUY; // Directly assign ALUY
|
|
||||||
default: Y = 8'b00000000; // Default case for safety
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,59 +0,0 @@
|
|||||||
$date
|
|
||||||
Sat Jan 18 17:21:23 2025
|
|
||||||
$end
|
|
||||||
$version
|
|
||||||
Icarus Verilog
|
|
||||||
$end
|
|
||||||
$timescale
|
|
||||||
1s
|
|
||||||
$end
|
|
||||||
$scope module selectorTB $end
|
|
||||||
$var wire 8 ! Y [7:0] $end
|
|
||||||
$var reg 4 " A [3:0] $end
|
|
||||||
$var reg 8 # ALUY [7:0] $end
|
|
||||||
$var reg 4 $ B [3:0] $end
|
|
||||||
$var reg 3 % opCodeA [2:0] $end
|
|
||||||
$var reg 2 & select [1:0] $end
|
|
||||||
$scope module uut $end
|
|
||||||
$var wire 4 ' A [3:0] $end
|
|
||||||
$var wire 8 ( ALUY [7:0] $end
|
|
||||||
$var wire 4 ) B [3:0] $end
|
|
||||||
$var wire 3 * opCodeA [2:0] $end
|
|
||||||
$var wire 2 + select [1:0] $end
|
|
||||||
$var reg 8 , Y [7:0] $end
|
|
||||||
$upscope $end
|
|
||||||
$upscope $end
|
|
||||||
$enddefinitions $end
|
|
||||||
#0
|
|
||||||
$dumpvars
|
|
||||||
b1 ,
|
|
||||||
b0 +
|
|
||||||
b111 *
|
|
||||||
b10 )
|
|
||||||
b11110000 (
|
|
||||||
b1 '
|
|
||||||
b0 &
|
|
||||||
b111 %
|
|
||||||
b10 $
|
|
||||||
b11110000 #
|
|
||||||
b1 "
|
|
||||||
b1 !
|
|
||||||
$end
|
|
||||||
#5
|
|
||||||
b10 !
|
|
||||||
b10 ,
|
|
||||||
b1 &
|
|
||||||
b1 +
|
|
||||||
#10
|
|
||||||
b111 !
|
|
||||||
b111 ,
|
|
||||||
b10 &
|
|
||||||
b10 +
|
|
||||||
b1110000 #
|
|
||||||
b1110000 (
|
|
||||||
#15
|
|
||||||
b1110000 !
|
|
||||||
b1110000 ,
|
|
||||||
b11 &
|
|
||||||
b11 +
|
|
||||||
#20
|
|
@ -1,28 +0,0 @@
|
|||||||
module selectorTB();
|
|
||||||
|
|
||||||
reg [1:0] select;
|
|
||||||
reg [3:0] A, B;
|
|
||||||
reg [7:0] ALUY;
|
|
||||||
reg [2:0] opCodeA;
|
|
||||||
wire [7:0] Y;
|
|
||||||
|
|
||||||
selector uut (
|
|
||||||
.select(select),
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.opCodeA(opCodeA),
|
|
||||||
.ALUY(ALUY),
|
|
||||||
.Y(Y)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("selector.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b00; #5;
|
|
||||||
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b01; #5;
|
|
||||||
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b10; #5;
|
|
||||||
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b11; #5;
|
|
||||||
$finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,22 +0,0 @@
|
|||||||
# Clock signal
|
|
||||||
NET "clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
|
|
||||||
|
|
||||||
# Slide Switches
|
|
||||||
NET "switches<0>" LOC = "L13" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
|
||||||
NET "switches<1>" LOC = "L14" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
|
||||||
NET "switches<2>" LOC = "H18" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
|
||||||
NET "switches<3>" LOC = "N17" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
|
||||||
|
|
||||||
# Rotary Encoder
|
|
||||||
NET "rot_a" LOC = "K18" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
|
||||||
NET "rot_b" LOC = "G18" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
|
||||||
NET "rot_center" LOC = "V16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
|
|
||||||
|
|
||||||
# LCD Interface
|
|
||||||
NET "lcd_e" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
||||||
NET "lcd_rs" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
||||||
NET "lcd_rw" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
||||||
NET "lcd_d<4>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
||||||
NET "lcd_d<5>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
||||||
NET "lcd_d<6>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
||||||
NET "lcd_d<7>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
|
@ -1,16 +0,0 @@
|
|||||||
module subtraction (
|
|
||||||
input [3:0] A, B,
|
|
||||||
input BorrowIN,
|
|
||||||
output [3:0] Y,
|
|
||||||
output BorrowOUT //Overflow signal'ini yani negatif gonderecek
|
|
||||||
);
|
|
||||||
|
|
||||||
wire [3:0] tempB;
|
|
||||||
|
|
||||||
// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
|
|
||||||
fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
|
|
||||||
fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
|
|
||||||
fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
|
|
||||||
fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,41 +0,0 @@
|
|||||||
module subtractionTB;
|
|
||||||
|
|
||||||
reg [3:0] A, B;
|
|
||||||
reg BorrowIN;
|
|
||||||
wire [3:0] Y;
|
|
||||||
wire BorrowOUT;
|
|
||||||
|
|
||||||
// Instantiate the subtraction module
|
|
||||||
subtraction uut (
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.BorrowIN(BorrowIN),
|
|
||||||
.Y(Y),
|
|
||||||
.BorrowOUT(BorrowOUT)
|
|
||||||
);
|
|
||||||
|
|
||||||
initial begin
|
|
||||||
$dumpfile("subtraction.vcd");
|
|
||||||
$dumpvars;
|
|
||||||
// Initialize inputs
|
|
||||||
A = 4'b0000; // Set A to 0
|
|
||||||
B = 4'b0000; // Set B to 0
|
|
||||||
BorrowIN = 0; // No borrow input
|
|
||||||
|
|
||||||
// Apply test cases
|
|
||||||
#10 A = 4'b0110; B = 4'b0010; BorrowIN = 0; // A = 6, B = 2
|
|
||||||
#10 A = 4'b0010; B = 4'b0110; BorrowIN = 0; // A = 2, B = 6
|
|
||||||
#10 A = 4'b1100; B = 4'b0100; BorrowIN = 0; // A = -4, B = 4
|
|
||||||
#10 A = 4'b1000; B = 4'b1000; BorrowIN = 0; // A = -8, B = -8
|
|
||||||
#10 A = 4'b1111; B = 4'b0001; BorrowIN = 1; // A = -1, B = 1, with borrow input
|
|
||||||
|
|
||||||
// Wait for the results
|
|
||||||
#10 $finish;
|
|
||||||
end
|
|
||||||
|
|
||||||
//initial begin
|
|
||||||
// Monitor the values of Y and overflow
|
|
||||||
// $monitor("At time %t: A = %b, B = %b, Y = %b, BorrowOut = %b, overflow = %b", $time, A, B, Y, BorrowOut, overflow);
|
|
||||||
//end
|
|
||||||
|
|
||||||
endmodule
|
|
@ -1,61 +0,0 @@
|
|||||||
module switchRotary(
|
|
||||||
input clk, // Clock signal
|
|
||||||
input [3:0] switches, // Slide switches SW3 to SW0
|
|
||||||
input rot_a, rot_b, // Rotary encoder signals
|
|
||||||
input rot_center, // Rotary encoder push button
|
|
||||||
output reg [3:0] A = 0, // Value of A
|
|
||||||
output reg [3:0] B = 0, // Value of B
|
|
||||||
output reg [2:0] opCode = 0 // Value of opCode
|
|
||||||
);
|
|
||||||
// Internal signals for rotary encoder
|
|
||||||
reg [1:0] rot_state = 2'b00;
|
|
||||||
reg [1:0] rot_prev = 2'b00;
|
|
||||||
|
|
||||||
// Selected register for modification
|
|
||||||
reg [1:0] selected = 2'b00; // 0 = A, 1 = B, 2 = opCode
|
|
||||||
|
|
||||||
// Debouncing for rotary center button
|
|
||||||
reg [15:0] debounce_counter = 0;
|
|
||||||
reg debounce_pressed = 0;
|
|
||||||
|
|
||||||
// Update selected register on rotary center press
|
|
||||||
always @(posedge clk) begin
|
|
||||||
if (rot_center && !debounce_pressed) begin
|
|
||||||
debounce_pressed <= 1;
|
|
||||||
selected <= selected + 1;
|
|
||||||
end
|
|
||||||
if (!rot_center) begin
|
|
||||||
debounce_pressed <= 0;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Handle rotary encoder signals
|
|
||||||
always @(posedge clk) begin
|
|
||||||
rot_prev <= rot_state;
|
|
||||||
rot_state <= {rot_a, rot_b};
|
|
||||||
|
|
||||||
// Detect clockwise or counterclockwise rotation
|
|
||||||
if (rot_prev == 2'b01 && rot_state == 2'b11) begin
|
|
||||||
case (selected)
|
|
||||||
2'b00: if (A < 15) A <= A + 1;
|
|
||||||
2'b01: if (B < 15) B <= B + 1;
|
|
||||||
2'b10: if (opCode < 7) opCode <= opCode + 1;
|
|
||||||
endcase
|
|
||||||
end else if (rot_prev == 2'b11 && rot_state == 2'b01) begin
|
|
||||||
case (selected)
|
|
||||||
2'b00: if (A > 0) A <= A - 1;
|
|
||||||
2'b01: if (B > 0) B <= B - 1;
|
|
||||||
2'b10: if (opCode > 0) opCode <= opCode - 1;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
// Update A, B, or opCode based on switches
|
|
||||||
always @(posedge clk) begin
|
|
||||||
case (switches)
|
|
||||||
4'b0001: A <= switches[3:0];
|
|
||||||
4'b0010: B <= switches[3:0];
|
|
||||||
4'b1000: opCode <= switches[2:0];
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
endmodule
|
|
@ -1,62 +0,0 @@
|
|||||||
module top (
|
|
||||||
input clk, // Clock signal
|
|
||||||
input [3:0] switches, // Slide switches SW3 to SW0
|
|
||||||
input rot_a, rot_b, // Rotary encoder signals
|
|
||||||
input rot_center, // Rotary encoder push button
|
|
||||||
output lcd_rs, // LCD Register Select
|
|
||||||
output lcd_rw, // LCD Read/Write
|
|
||||||
output lcd_e, // LCD Enable
|
|
||||||
output [7:4] lcd_d // LCD Data
|
|
||||||
);
|
|
||||||
// Internal signals
|
|
||||||
wire [3:0] A;
|
|
||||||
wire [3:0] B;
|
|
||||||
wire [2:0] opCode;
|
|
||||||
wire [7:0] Y;
|
|
||||||
wire [4:0] mem_addr;
|
|
||||||
wire [7:0] mem_bus;
|
|
||||||
|
|
||||||
// ALU Instance
|
|
||||||
ALU alu_inst (
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.CarryIN(1'b0), // No carry-in for this implementation
|
|
||||||
.opCodeA(opCode),
|
|
||||||
.Y(Y),
|
|
||||||
.CarryOUT(), // Unused output
|
|
||||||
.overflow() // Unused output
|
|
||||||
);
|
|
||||||
|
|
||||||
// Switch and Rotary Controller
|
|
||||||
switch_and_rotary switch_rotary_inst (
|
|
||||||
.clk(clk),
|
|
||||||
.switches(switches),
|
|
||||||
.rot_a(rot_a),
|
|
||||||
.rot_b(rot_b),
|
|
||||||
.rot_center(rot_center),
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.opCode(opCode)
|
|
||||||
);
|
|
||||||
|
|
||||||
// Character Memory
|
|
||||||
char_mem char_mem_inst (
|
|
||||||
.addr(mem_addr),
|
|
||||||
.bus(mem_bus),
|
|
||||||
.A(A),
|
|
||||||
.B(B),
|
|
||||||
.opCode(opCode),
|
|
||||||
.Y(Y)
|
|
||||||
);
|
|
||||||
|
|
||||||
// LCD Controller
|
|
||||||
lcd lcd_inst (
|
|
||||||
.clk(clk),
|
|
||||||
.lcd_rs(lcd_rs),
|
|
||||||
.lcd_rw(lcd_rw),
|
|
||||||
.lcd_e(lcd_e),
|
|
||||||
.lcd_d(lcd_d),
|
|
||||||
.mem_addr(mem_addr),
|
|
||||||
.mem_bus(mem_bus)
|
|
||||||
);
|
|
||||||
endmodule
|
|
2181
tangTest/ALU
Normal file
2181
tangTest/ALU
Normal file
File diff suppressed because it is too large
Load Diff
1086
tangTest/ALU.vcd
Normal file
1086
tangTest/ALU.vcd
Normal file
File diff suppressed because it is too large
Load Diff
26
tangTest/ALUtb.v
Normal file
26
tangTest/ALUtb.v
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
module ALUtb();
|
||||||
|
|
||||||
|
reg [3:0] A,B;
|
||||||
|
reg CarryIN;
|
||||||
|
reg [2:0] opCodeA;
|
||||||
|
wire CarryOUT, overflow;
|
||||||
|
wire [7:0] Y;
|
||||||
|
|
||||||
|
ALU uut (
|
||||||
|
.A(A),
|
||||||
|
.B(B),
|
||||||
|
.CarryIN(CarryIN),
|
||||||
|
.opCodeA(opCodeA),
|
||||||
|
.CarryOUT(CarryOUT),
|
||||||
|
.overflow(overflow),
|
||||||
|
.Y(Y)
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$dumpfile("ALU.vcd");
|
||||||
|
$dumpvars;
|
||||||
|
A = 4'b1111; B = 4'b0001; CarryIN = 1'b0; opCodeA = 3'b001; #5;
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
2220
tangTest/bttn
Normal file
2220
tangTest/bttn
Normal file
File diff suppressed because it is too large
Load Diff
@ -5,7 +5,7 @@
|
|||||||
//Part Number: GW2A-LV18PG256C8/I7
|
//Part Number: GW2A-LV18PG256C8/I7
|
||||||
//Device: GW2A-18
|
//Device: GW2A-18
|
||||||
//Device Version: C
|
//Device Version: C
|
||||||
//Created Time: Mon 01 20 17:48:00 2025
|
//Created Time: Sat 01 18 21:56:09 2025
|
||||||
|
|
||||||
IO_LOC "Y[11]" B12;
|
IO_LOC "Y[11]" B12;
|
||||||
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
IO_PORT "Y[11]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
||||||
@ -31,12 +31,6 @@ IO_LOC "Y[1]" T7;
|
|||||||
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
IO_PORT "Y[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
||||||
IO_LOC "Y[0]" P6;
|
IO_LOC "Y[0]" P6;
|
||||||
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
IO_PORT "Y[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
||||||
IO_LOC "leds[1]" L14;
|
|
||||||
IO_PORT "leds[1]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
|
||||||
IO_LOC "leds[0]" L16;
|
|
||||||
IO_PORT "leds[0]" IO_TYPE=LVCMOS18 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=1.8;
|
|
||||||
IO_LOC "Cin" E9;
|
|
||||||
IO_PORT "Cin" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
|
|
||||||
IO_LOC "select[1]" A14;
|
IO_LOC "select[1]" A14;
|
||||||
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
|
IO_PORT "select[1]" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
|
||||||
IO_LOC "select[0]" A15;
|
IO_LOC "select[0]" A15;
|
@ -2,18 +2,19 @@ module bttn (
|
|||||||
input [3:0] A, B,
|
input [3:0] A, B,
|
||||||
input [2:0] opCodeA,
|
input [2:0] opCodeA,
|
||||||
input [1:0] select,
|
input [1:0] select,
|
||||||
input Cin,
|
output [1:0] led,
|
||||||
output [1:0] leds,
|
|
||||||
output [11:0] Y
|
output [11:0] Y
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
wire wire1, wire2;
|
wire wire1, wire2;
|
||||||
wire [11:0] selectY;
|
wire [11:0] selectY;
|
||||||
ALU a1(.A(A), .B(B), .opCodeA(opCodeA), .CarryIN(Cin), .bcd(selectY), .CarryOUT(wire2), .overflow(wire1));
|
ALU a1( .A(A),
|
||||||
|
.B(B),
|
||||||
|
.opCodeA(opCodeA),
|
||||||
|
.CarryIN(1'b0),
|
||||||
|
.bcd(selectY),
|
||||||
|
.CarryOUT(led[0]),
|
||||||
|
.overflow(led[1]));
|
||||||
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
|
selector s1(.A(A), .B(B), .opCodeA(opCodeA), .select(select), .ALUY(selectY), .Y(Y));
|
||||||
|
|
||||||
assign leds[0] = ~wire1;
|
|
||||||
assign leds[1] = ~wire2;
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
1493
tangTest/bttn.vcd
Normal file
1493
tangTest/bttn.vcd
Normal file
File diff suppressed because it is too large
Load Diff
28
tangTest/bttnTB.v
Normal file
28
tangTest/bttnTB.v
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
module bttnTB();
|
||||||
|
|
||||||
|
reg [3:0] A,B;
|
||||||
|
reg [2:0] opCodeA;
|
||||||
|
reg [1:0] select;
|
||||||
|
wire [1:0] led;
|
||||||
|
wire [11:0] Y;
|
||||||
|
|
||||||
|
bttn uut (
|
||||||
|
.A(A),
|
||||||
|
.B(B),
|
||||||
|
.opCodeA(opCodeA),
|
||||||
|
.select(select),
|
||||||
|
.led(led),
|
||||||
|
.Y(Y)
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$dumpfile("bttn.vcd");
|
||||||
|
$dumpvars;
|
||||||
|
A = 4'b1111; B = 4'b1111; opCodeA = 3'b000; select = 2'b01; #5;
|
||||||
|
A = 4'b0000; B = 4'b1111; opCodeA = 3'b001; select = 2'b01; #5;
|
||||||
|
A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b01; #5;
|
||||||
|
A = 4'b1111; B = 4'b0001; opCodeA = 3'b001; select = 2'b11; #5;
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
782
tangTest/mult
Normal file
782
tangTest/mult
Normal file
@ -0,0 +1,782 @@
|
|||||||
|
#! /usr/bin/vvp
|
||||||
|
:ivl_version "11.0 (stable)";
|
||||||
|
:ivl_delay_selection "TYPICAL";
|
||||||
|
:vpi_time_precision + 0;
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||||
|
S_0x560808805dd0 .scope module, "multTB" "multTB" 2 1;
|
||||||
|
.timescale 0 0;
|
||||||
|
v0x56080883b1b0_0 .var "A", 3 0;
|
||||||
|
v0x56080883b2a0_0 .var "B", 3 0;
|
||||||
|
v0x56080883b370_0 .net "Y", 7 0, L_0x560808846dd0; 1 drivers
|
||||||
|
S_0x560808804330 .scope module, "uut" "multiplier" 2 6, 3 1 0, S_0x560808805dd0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 4 "A";
|
||||||
|
.port_info 1 /INPUT 4 "B";
|
||||||
|
.port_info 2 /OUTPUT 8 "Y";
|
||||||
|
L_0x56080883b470 .functor AND 1, L_0x56080883b570, L_0x56080883b660, C4<1>, C4<1>;
|
||||||
|
L_0x56080883b7a0 .functor AND 1, L_0x56080883b810, L_0x56080883b900, C4<1>, C4<1>;
|
||||||
|
L_0x56080883ba20 .functor AND 1, L_0x56080883ba90, L_0x56080883bb80, C4<1>, C4<1>;
|
||||||
|
L_0x56080883bc60 .functor AND 1, L_0x56080883bd00, L_0x56080883bda0, C4<1>, C4<1>;
|
||||||
|
L_0x7f3ea6b4d018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x56080883c0c0 .functor NOT 1, L_0x7f3ea6b4d018, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x56080883c1d0 .functor AND 1, L_0x56080883c280, L_0x56080883c3d0, C4<1>, C4<1>;
|
||||||
|
L_0x56080883c470 .functor AND 1, L_0x56080883c4e0, L_0x56080883c640, C4<1>, C4<1>;
|
||||||
|
L_0x56080883c730 .functor AND 1, L_0x56080883c7f0, L_0x56080883c960, C4<1>, C4<1>;
|
||||||
|
L_0x56080883c5d0 .functor AND 1, L_0x56080883cd10, L_0x56080883ce00, C4<1>, C4<1>;
|
||||||
|
L_0x56080883ef10 .functor AND 1, L_0x56080883f360, L_0x56080883cef0, C4<1>, C4<1>;
|
||||||
|
L_0x56080883f4b0 .functor AND 1, L_0x56080883f520, L_0x56080883f680, C4<1>, C4<1>;
|
||||||
|
L_0x56080883f720 .functor AND 1, L_0x56080883f800, L_0x56080883f9c0, C4<1>, C4<1>;
|
||||||
|
L_0x56080883fd70 .functor AND 1, L_0x56080883fe30, L_0x56080883ff20, C4<1>, C4<1>;
|
||||||
|
L_0x5608088423d0 .functor AND 1, L_0x5608088429c0, L_0x560808842a60, C4<1>, C4<1>;
|
||||||
|
L_0x56080883f790 .functor AND 1, L_0x560808842c10, L_0x560808842cb0, C4<1>, C4<1>;
|
||||||
|
L_0x560808842ec0 .functor AND 1, L_0x560808842fc0, L_0x5608088430b0, C4<1>, C4<1>;
|
||||||
|
L_0x5608088435d0 .functor AND 1, L_0x560808843690, L_0x5608088438c0, C4<1>, C4<1>;
|
||||||
|
L_0x7f3ea6b4d138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x560808845900 .functor OR 1, L_0x560808845f60, L_0x7f3ea6b4d138, C4<0>, C4<0>;
|
||||||
|
L_0x7f3ea6b4d180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x560808846160 .functor OR 1, L_0x5608088461d0, L_0x7f3ea6b4d180, C4<0>, C4<0>;
|
||||||
|
L_0x7f3ea6b4d1c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x560808846310 .functor OR 1, L_0x560808845ec0, L_0x7f3ea6b4d1c8, C4<0>, C4<0>;
|
||||||
|
L_0x7f3ea6b4d210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x560808846690 .functor OR 1, L_0x560808846700, L_0x7f3ea6b4d210, C4<0>, C4<0>;
|
||||||
|
L_0x7f3ea6b4d258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x560808846840 .functor OR 1, L_0x560808846970, L_0x7f3ea6b4d258, C4<0>, C4<0>;
|
||||||
|
L_0x7f3ea6b4d2a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x560808846c70 .functor OR 1, L_0x560808846ce0, L_0x7f3ea6b4d2a0, C4<0>, C4<0>;
|
||||||
|
L_0x7f3ea6b4d2e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x5608088472d0 .functor OR 1, L_0x560808847460, L_0x7f3ea6b4d2e8, C4<0>, C4<0>;
|
||||||
|
v0x560808836240_0 .net "A", 3 0, v0x56080883b1b0_0; 1 drivers
|
||||||
|
v0x560808836340_0 .net "B", 3 0, v0x56080883b2a0_0; 1 drivers
|
||||||
|
v0x560808836420_0 .net "S0", 4 0, L_0x56080883f1d0; 1 drivers
|
||||||
|
v0x5608088364e0_0 .net "S1", 4 0, L_0x560808842710; 1 drivers
|
||||||
|
v0x5608088365c0_0 .net "S2", 4 0, L_0x560808845d90; 1 drivers
|
||||||
|
v0x5608088366f0_0 .net "Y", 7 0, L_0x560808846dd0; alias, 1 drivers
|
||||||
|
v0x5608088367d0_0 .net *"_ivl_1", 0 0, L_0x56080883b470; 1 drivers
|
||||||
|
v0x5608088368b0_0 .net *"_ivl_10", 0 0, L_0x56080883b810; 1 drivers
|
||||||
|
v0x560808836990_0 .net *"_ivl_101", 0 0, L_0x560808842a60; 1 drivers
|
||||||
|
v0x560808836a70_0 .net *"_ivl_102", 0 0, L_0x56080883f790; 1 drivers
|
||||||
|
v0x560808836b50_0 .net *"_ivl_105", 0 0, L_0x560808842c10; 1 drivers
|
||||||
|
v0x560808836c30_0 .net *"_ivl_107", 0 0, L_0x560808842cb0; 1 drivers
|
||||||
|
v0x560808836d10_0 .net *"_ivl_108", 0 0, L_0x560808842ec0; 1 drivers
|
||||||
|
v0x560808836df0_0 .net *"_ivl_111", 0 0, L_0x560808842fc0; 1 drivers
|
||||||
|
v0x560808836ed0_0 .net *"_ivl_113", 0 0, L_0x5608088430b0; 1 drivers
|
||||||
|
v0x560808836fb0_0 .net *"_ivl_114", 0 0, L_0x5608088435d0; 1 drivers
|
||||||
|
v0x560808837090_0 .net *"_ivl_118", 0 0, L_0x560808843690; 1 drivers
|
||||||
|
v0x560808837170_0 .net *"_ivl_12", 0 0, L_0x56080883b900; 1 drivers
|
||||||
|
v0x560808837250_0 .net *"_ivl_120", 0 0, L_0x5608088438c0; 1 drivers
|
||||||
|
v0x560808837330_0 .net *"_ivl_13", 0 0, L_0x56080883ba20; 1 drivers
|
||||||
|
v0x560808837410_0 .net *"_ivl_130", 0 0, L_0x560808845900; 1 drivers
|
||||||
|
v0x5608088374f0_0 .net *"_ivl_133", 0 0, L_0x560808845f60; 1 drivers
|
||||||
|
v0x5608088375d0_0 .net/2u *"_ivl_134", 0 0, L_0x7f3ea6b4d138; 1 drivers
|
||||||
|
v0x5608088376b0_0 .net *"_ivl_136", 0 0, L_0x560808846160; 1 drivers
|
||||||
|
v0x560808837790_0 .net *"_ivl_139", 0 0, L_0x5608088461d0; 1 drivers
|
||||||
|
v0x560808837870_0 .net/2u *"_ivl_140", 0 0, L_0x7f3ea6b4d180; 1 drivers
|
||||||
|
v0x560808837950_0 .net *"_ivl_142", 0 0, L_0x560808846310; 1 drivers
|
||||||
|
v0x560808837a30_0 .net *"_ivl_145", 0 0, L_0x560808845ec0; 1 drivers
|
||||||
|
v0x560808837b10_0 .net/2u *"_ivl_146", 0 0, L_0x7f3ea6b4d1c8; 1 drivers
|
||||||
|
v0x560808837bf0_0 .net *"_ivl_148", 0 0, L_0x560808846690; 1 drivers
|
||||||
|
v0x560808837cd0_0 .net *"_ivl_151", 0 0, L_0x560808846700; 1 drivers
|
||||||
|
v0x560808837db0_0 .net/2u *"_ivl_152", 0 0, L_0x7f3ea6b4d210; 1 drivers
|
||||||
|
v0x560808837e90_0 .net *"_ivl_154", 0 0, L_0x560808846840; 1 drivers
|
||||||
|
v0x560808838180_0 .net *"_ivl_157", 0 0, L_0x560808846970; 1 drivers
|
||||||
|
v0x560808838260_0 .net/2u *"_ivl_158", 0 0, L_0x7f3ea6b4d258; 1 drivers
|
||||||
|
v0x560808838340_0 .net *"_ivl_16", 0 0, L_0x56080883ba90; 1 drivers
|
||||||
|
v0x560808838420_0 .net *"_ivl_160", 0 0, L_0x560808846c70; 1 drivers
|
||||||
|
v0x560808838500_0 .net *"_ivl_163", 0 0, L_0x560808846ce0; 1 drivers
|
||||||
|
v0x5608088385e0_0 .net/2u *"_ivl_164", 0 0, L_0x7f3ea6b4d2a0; 1 drivers
|
||||||
|
v0x5608088386c0_0 .net *"_ivl_166", 0 0, L_0x5608088472d0; 1 drivers
|
||||||
|
v0x5608088387a0_0 .net *"_ivl_170", 0 0, L_0x560808847460; 1 drivers
|
||||||
|
v0x560808838880_0 .net/2u *"_ivl_171", 0 0, L_0x7f3ea6b4d2e8; 1 drivers
|
||||||
|
v0x560808838960_0 .net *"_ivl_18", 0 0, L_0x56080883bb80; 1 drivers
|
||||||
|
v0x560808838a40_0 .net *"_ivl_19", 0 0, L_0x56080883bc60; 1 drivers
|
||||||
|
v0x560808838b20_0 .net *"_ivl_22", 0 0, L_0x56080883bd00; 1 drivers
|
||||||
|
v0x560808838c00_0 .net *"_ivl_24", 0 0, L_0x56080883bda0; 1 drivers
|
||||||
|
v0x560808838ce0_0 .net *"_ivl_25", 0 0, L_0x56080883c0c0; 1 drivers
|
||||||
|
v0x560808838dc0_0 .net/2u *"_ivl_28", 0 0, L_0x7f3ea6b4d018; 1 drivers
|
||||||
|
v0x560808838ea0_0 .net *"_ivl_30", 0 0, L_0x56080883c1d0; 1 drivers
|
||||||
|
v0x560808838f80_0 .net *"_ivl_33", 0 0, L_0x56080883c280; 1 drivers
|
||||||
|
v0x560808839060_0 .net *"_ivl_35", 0 0, L_0x56080883c3d0; 1 drivers
|
||||||
|
v0x560808839140_0 .net *"_ivl_36", 0 0, L_0x56080883c470; 1 drivers
|
||||||
|
v0x560808839220_0 .net *"_ivl_39", 0 0, L_0x56080883c4e0; 1 drivers
|
||||||
|
v0x560808839300_0 .net *"_ivl_4", 0 0, L_0x56080883b570; 1 drivers
|
||||||
|
v0x5608088393e0_0 .net *"_ivl_41", 0 0, L_0x56080883c640; 1 drivers
|
||||||
|
v0x5608088394c0_0 .net *"_ivl_42", 0 0, L_0x56080883c730; 1 drivers
|
||||||
|
v0x5608088395a0_0 .net *"_ivl_45", 0 0, L_0x56080883c7f0; 1 drivers
|
||||||
|
v0x560808839680_0 .net *"_ivl_47", 0 0, L_0x56080883c960; 1 drivers
|
||||||
|
v0x560808839760_0 .net *"_ivl_48", 0 0, L_0x56080883c5d0; 1 drivers
|
||||||
|
v0x560808839840_0 .net *"_ivl_52", 0 0, L_0x56080883cd10; 1 drivers
|
||||||
|
v0x560808839920_0 .net *"_ivl_54", 0 0, L_0x56080883ce00; 1 drivers
|
||||||
|
v0x560808839a00_0 .net *"_ivl_6", 0 0, L_0x56080883b660; 1 drivers
|
||||||
|
v0x560808839ae0_0 .net *"_ivl_62", 0 0, L_0x56080883ef10; 1 drivers
|
||||||
|
v0x560808839bc0_0 .net *"_ivl_65", 0 0, L_0x56080883f360; 1 drivers
|
||||||
|
v0x560808839ca0_0 .net *"_ivl_67", 0 0, L_0x56080883cef0; 1 drivers
|
||||||
|
v0x56080883a190_0 .net *"_ivl_68", 0 0, L_0x56080883f4b0; 1 drivers
|
||||||
|
v0x56080883a270_0 .net *"_ivl_7", 0 0, L_0x56080883b7a0; 1 drivers
|
||||||
|
v0x56080883a350_0 .net *"_ivl_71", 0 0, L_0x56080883f520; 1 drivers
|
||||||
|
v0x56080883a430_0 .net *"_ivl_73", 0 0, L_0x56080883f680; 1 drivers
|
||||||
|
v0x56080883a510_0 .net *"_ivl_74", 0 0, L_0x56080883f720; 1 drivers
|
||||||
|
v0x56080883a5f0_0 .net *"_ivl_77", 0 0, L_0x56080883f800; 1 drivers
|
||||||
|
v0x56080883a6d0_0 .net *"_ivl_79", 0 0, L_0x56080883f9c0; 1 drivers
|
||||||
|
v0x56080883a7b0_0 .net *"_ivl_80", 0 0, L_0x56080883fd70; 1 drivers
|
||||||
|
v0x56080883a890_0 .net *"_ivl_84", 0 0, L_0x56080883fe30; 1 drivers
|
||||||
|
v0x56080883a970_0 .net *"_ivl_86", 0 0, L_0x56080883ff20; 1 drivers
|
||||||
|
v0x56080883aa50_0 .net *"_ivl_96", 0 0, L_0x5608088423d0; 1 drivers
|
||||||
|
v0x56080883ab30_0 .net *"_ivl_99", 0 0, L_0x5608088429c0; 1 drivers
|
||||||
|
v0x56080883ac10_0 .net "a0", 3 0, L_0x56080883ca50; 1 drivers
|
||||||
|
v0x56080883acd0_0 .net "a1", 3 0, L_0x56080883fab0; 1 drivers
|
||||||
|
v0x56080883ada0_0 .net "a2", 3 0, L_0x560808842da0; 1 drivers
|
||||||
|
v0x56080883ae70_0 .net "b0", 3 0, L_0x56080883bee0; 1 drivers
|
||||||
|
v0x56080883af40_0 .net "overflow0", 0 0, L_0x56080883f020; 1 drivers
|
||||||
|
v0x56080883b010_0 .net "overflow1", 0 0, L_0x5608088424e0; 1 drivers
|
||||||
|
v0x56080883b0e0_0 .net "overflow2", 0 0, L_0x560808845a10; 1 drivers
|
||||||
|
L_0x56080883b570 .part v0x56080883b1b0_0, 0, 1;
|
||||||
|
L_0x56080883b660 .part v0x56080883b2a0_0, 0, 1;
|
||||||
|
L_0x56080883b810 .part v0x56080883b1b0_0, 1, 1;
|
||||||
|
L_0x56080883b900 .part v0x56080883b2a0_0, 0, 1;
|
||||||
|
L_0x56080883ba90 .part v0x56080883b1b0_0, 2, 1;
|
||||||
|
L_0x56080883bb80 .part v0x56080883b2a0_0, 0, 1;
|
||||||
|
L_0x56080883bd00 .part v0x56080883b1b0_0, 3, 1;
|
||||||
|
L_0x56080883bda0 .part v0x56080883b2a0_0, 0, 1;
|
||||||
|
L_0x56080883bee0 .concat8 [ 1 1 1 1], L_0x56080883b7a0, L_0x56080883ba20, L_0x56080883bc60, L_0x56080883c0c0;
|
||||||
|
L_0x56080883c280 .part v0x56080883b1b0_0, 0, 1;
|
||||||
|
L_0x56080883c3d0 .part v0x56080883b2a0_0, 1, 1;
|
||||||
|
L_0x56080883c4e0 .part v0x56080883b1b0_0, 1, 1;
|
||||||
|
L_0x56080883c640 .part v0x56080883b2a0_0, 1, 1;
|
||||||
|
L_0x56080883c7f0 .part v0x56080883b1b0_0, 2, 1;
|
||||||
|
L_0x56080883c960 .part v0x56080883b2a0_0, 1, 1;
|
||||||
|
L_0x56080883ca50 .concat8 [ 1 1 1 1], L_0x56080883c1d0, L_0x56080883c470, L_0x56080883c730, L_0x56080883c5d0;
|
||||||
|
L_0x56080883cd10 .part v0x56080883b1b0_0, 3, 1;
|
||||||
|
L_0x56080883ce00 .part v0x56080883b2a0_0, 1, 1;
|
||||||
|
L_0x56080883f1d0 .concat8 [ 4 1 0 0], L_0x56080883ef80, L_0x56080883e990;
|
||||||
|
L_0x56080883f360 .part v0x56080883b1b0_0, 0, 1;
|
||||||
|
L_0x56080883cef0 .part v0x56080883b2a0_0, 2, 1;
|
||||||
|
L_0x56080883f520 .part v0x56080883b1b0_0, 1, 1;
|
||||||
|
L_0x56080883f680 .part v0x56080883b2a0_0, 2, 1;
|
||||||
|
L_0x56080883f800 .part v0x56080883b1b0_0, 2, 1;
|
||||||
|
L_0x56080883f9c0 .part v0x56080883b2a0_0, 2, 1;
|
||||||
|
L_0x56080883fab0 .concat8 [ 1 1 1 1], L_0x56080883ef10, L_0x56080883f4b0, L_0x56080883f720, L_0x56080883fd70;
|
||||||
|
L_0x56080883fe30 .part v0x56080883b1b0_0, 3, 1;
|
||||||
|
L_0x56080883ff20 .part v0x56080883b2a0_0, 2, 1;
|
||||||
|
L_0x560808842670 .part L_0x56080883f1d0, 1, 4;
|
||||||
|
L_0x560808842710 .concat8 [ 4 1 0 0], L_0x560808842440, L_0x560808841dc0;
|
||||||
|
L_0x5608088429c0 .part v0x56080883b1b0_0, 0, 1;
|
||||||
|
L_0x560808842a60 .part v0x56080883b2a0_0, 3, 1;
|
||||||
|
L_0x560808842c10 .part v0x56080883b1b0_0, 1, 1;
|
||||||
|
L_0x560808842cb0 .part v0x56080883b2a0_0, 3, 1;
|
||||||
|
L_0x560808842fc0 .part v0x56080883b1b0_0, 2, 1;
|
||||||
|
L_0x5608088430b0 .part v0x56080883b2a0_0, 3, 1;
|
||||||
|
L_0x560808842da0 .concat8 [ 1 1 1 1], L_0x5608088423d0, L_0x56080883f790, L_0x560808842ec0, L_0x5608088435d0;
|
||||||
|
L_0x560808843690 .part v0x56080883b1b0_0, 3, 1;
|
||||||
|
L_0x5608088438c0 .part v0x56080883b2a0_0, 3, 1;
|
||||||
|
L_0x560808845ba0 .part L_0x560808842710, 1, 4;
|
||||||
|
L_0x560808845d90 .concat8 [ 4 1 0 0], L_0x560808845970, L_0x560808845330;
|
||||||
|
L_0x560808845f60 .part L_0x56080883f1d0, 0, 1;
|
||||||
|
L_0x5608088461d0 .part L_0x560808842710, 0, 1;
|
||||||
|
L_0x560808845ec0 .part L_0x560808845d90, 0, 1;
|
||||||
|
L_0x560808846700 .part L_0x560808845d90, 1, 1;
|
||||||
|
L_0x560808846970 .part L_0x560808845d90, 2, 1;
|
||||||
|
L_0x560808846ce0 .part L_0x560808845d90, 3, 1;
|
||||||
|
LS_0x560808846dd0_0_0 .concat8 [ 1 1 1 1], L_0x56080883b470, L_0x560808845900, L_0x560808846160, L_0x560808846310;
|
||||||
|
LS_0x560808846dd0_0_4 .concat8 [ 1 1 1 1], L_0x560808846690, L_0x560808846840, L_0x560808846c70, L_0x5608088472d0;
|
||||||
|
L_0x560808846dd0 .concat8 [ 4 4 0 0], LS_0x560808846dd0_0_0, LS_0x560808846dd0_0_4;
|
||||||
|
L_0x560808847460 .part L_0x560808845d90, 4, 1;
|
||||||
|
S_0x5608087fbca0 .scope module, "add0" "addition" 3 26, 4 1 0, S_0x560808804330;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 4 "A";
|
||||||
|
.port_info 1 /INPUT 4 "B";
|
||||||
|
.port_info 2 /INPUT 1 "CarryIN";
|
||||||
|
.port_info 3 /OUTPUT 4 "Y";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryOUT";
|
||||||
|
.port_info 5 /OUTPUT 1 "overflow";
|
||||||
|
L_0x56080883f020 .functor XOR 1, L_0x56080883f090, L_0x56080883e990, C4<0>, C4<0>;
|
||||||
|
v0x560808829b90_0 .net "A", 3 0, L_0x56080883ca50; alias, 1 drivers
|
||||||
|
v0x560808829c70_0 .net "B", 3 0, L_0x56080883bee0; alias, 1 drivers
|
||||||
|
v0x560808829d50_0 .net "Carry4", 2 0, L_0x56080883e400; 1 drivers
|
||||||
|
L_0x7f3ea6b4d060 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
v0x560808829e10_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d060; 1 drivers
|
||||||
|
v0x560808829f00_0 .net "CarryOUT", 0 0, L_0x56080883e990; 1 drivers
|
||||||
|
v0x560808829ff0_0 .net "Y", 3 0, L_0x56080883ef80; 1 drivers
|
||||||
|
v0x56080882a0b0_0 .net *"_ivl_39", 0 0, L_0x56080883f090; 1 drivers
|
||||||
|
v0x56080882a190_0 .net "overflow", 0 0, L_0x56080883f020; alias, 1 drivers
|
||||||
|
L_0x56080883d300 .part L_0x56080883ca50, 0, 1;
|
||||||
|
L_0x56080883d3a0 .part L_0x56080883bee0, 0, 1;
|
||||||
|
L_0x56080883d830 .part L_0x56080883ca50, 1, 1;
|
||||||
|
L_0x56080883d9f0 .part L_0x56080883bee0, 1, 1;
|
||||||
|
L_0x56080883dbb0 .part L_0x56080883e400, 0, 1;
|
||||||
|
L_0x56080883dfe0 .part L_0x56080883ca50, 2, 1;
|
||||||
|
L_0x56080883e150 .part L_0x56080883bee0, 2, 1;
|
||||||
|
L_0x56080883e280 .part L_0x56080883e400, 1, 1;
|
||||||
|
L_0x56080883e400 .concat8 [ 1 1 1 0], L_0x56080883d290, L_0x56080883d7c0, L_0x56080883df50;
|
||||||
|
L_0x56080883ea90 .part L_0x56080883ca50, 3, 1;
|
||||||
|
L_0x56080883ec20 .part L_0x56080883bee0, 3, 1;
|
||||||
|
L_0x56080883ed50 .part L_0x56080883e400, 2, 1;
|
||||||
|
L_0x56080883ef80 .concat8 [ 1 1 1 1], L_0x56080883d220, L_0x56080883d700, L_0x56080883dec0, L_0x56080883e8b0;
|
||||||
|
L_0x56080883f090 .part L_0x56080883e400, 2, 1;
|
||||||
|
S_0x5608087fa200 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608087fbca0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x56080883d290 .functor OR 1, L_0x56080883cf90, L_0x56080883d160, C4<0>, C4<0>;
|
||||||
|
v0x560808825840_0 .net "A", 0 0, L_0x56080883d300; 1 drivers
|
||||||
|
v0x560808825900_0 .net "B", 0 0, L_0x56080883d3a0; 1 drivers
|
||||||
|
v0x5608088259d0_0 .net "Carry", 0 0, L_0x7f3ea6b4d060; alias, 1 drivers
|
||||||
|
v0x560808825ad0_0 .net "CarryO", 0 0, L_0x56080883d290; 1 drivers
|
||||||
|
v0x560808825b70_0 .net "Sum", 0 0, L_0x56080883d220; 1 drivers
|
||||||
|
v0x560808825c60_0 .net "and1", 0 0, L_0x56080883cf90; 1 drivers
|
||||||
|
v0x560808825d30_0 .net "and2", 0 0, L_0x56080883d160; 1 drivers
|
||||||
|
v0x560808825e00_0 .net "xor1", 0 0, L_0x56080883d0f0; 1 drivers
|
||||||
|
S_0x5608087f1eb0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x5608087fa200;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883cf90 .functor AND 1, L_0x56080883d300, L_0x56080883d3a0, C4<1>, C4<1>;
|
||||||
|
L_0x56080883d0f0 .functor XOR 1, L_0x56080883d300, L_0x56080883d3a0, C4<0>, C4<0>;
|
||||||
|
v0x56080880a2e0_0 .net "A", 0 0, L_0x56080883d300; alias, 1 drivers
|
||||||
|
v0x560808809740_0 .net "B", 0 0, L_0x56080883d3a0; alias, 1 drivers
|
||||||
|
v0x560808808a00_0 .net "Carry", 0 0, L_0x56080883cf90; alias, 1 drivers
|
||||||
|
v0x56080878a680_0 .net "Sum", 0 0, L_0x56080883d0f0; alias, 1 drivers
|
||||||
|
S_0x5608088252c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x5608087fa200;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883d160 .functor AND 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<1>, C4<1>;
|
||||||
|
L_0x56080883d220 .functor XOR 1, L_0x56080883d0f0, L_0x7f3ea6b4d060, C4<0>, C4<0>;
|
||||||
|
v0x5608088254c0_0 .net "A", 0 0, L_0x56080883d0f0; alias, 1 drivers
|
||||||
|
v0x560808825560_0 .net "B", 0 0, L_0x7f3ea6b4d060; alias, 1 drivers
|
||||||
|
v0x560808825600_0 .net "Carry", 0 0, L_0x56080883d160; alias, 1 drivers
|
||||||
|
v0x5608088256d0_0 .net "Sum", 0 0, L_0x56080883d220; alias, 1 drivers
|
||||||
|
S_0x560808825ef0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608087fbca0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x56080883d7c0 .functor OR 1, L_0x56080883d4d0, L_0x56080883d5b0, C4<0>, C4<0>;
|
||||||
|
v0x560808826c70_0 .net "A", 0 0, L_0x56080883d830; 1 drivers
|
||||||
|
v0x560808826d30_0 .net "B", 0 0, L_0x56080883d9f0; 1 drivers
|
||||||
|
v0x560808826e00_0 .net "Carry", 0 0, L_0x56080883dbb0; 1 drivers
|
||||||
|
v0x560808826f00_0 .net "CarryO", 0 0, L_0x56080883d7c0; 1 drivers
|
||||||
|
v0x560808826fa0_0 .net "Sum", 0 0, L_0x56080883d700; 1 drivers
|
||||||
|
v0x560808827090_0 .net "and1", 0 0, L_0x56080883d4d0; 1 drivers
|
||||||
|
v0x560808827160_0 .net "and2", 0 0, L_0x56080883d5b0; 1 drivers
|
||||||
|
v0x560808827230_0 .net "xor1", 0 0, L_0x56080883d540; 1 drivers
|
||||||
|
S_0x5608088260d0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808825ef0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883d4d0 .functor AND 1, L_0x56080883d830, L_0x56080883d9f0, C4<1>, C4<1>;
|
||||||
|
L_0x56080883d540 .functor XOR 1, L_0x56080883d830, L_0x56080883d9f0, C4<0>, C4<0>;
|
||||||
|
v0x5608088262e0_0 .net "A", 0 0, L_0x56080883d830; alias, 1 drivers
|
||||||
|
v0x5608088263c0_0 .net "B", 0 0, L_0x56080883d9f0; alias, 1 drivers
|
||||||
|
v0x560808826480_0 .net "Carry", 0 0, L_0x56080883d4d0; alias, 1 drivers
|
||||||
|
v0x560808826550_0 .net "Sum", 0 0, L_0x56080883d540; alias, 1 drivers
|
||||||
|
S_0x5608088266c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808825ef0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883d5b0 .functor AND 1, L_0x56080883d540, L_0x56080883dbb0, C4<1>, C4<1>;
|
||||||
|
L_0x56080883d700 .functor XOR 1, L_0x56080883d540, L_0x56080883dbb0, C4<0>, C4<0>;
|
||||||
|
v0x5608088268c0_0 .net "A", 0 0, L_0x56080883d540; alias, 1 drivers
|
||||||
|
v0x560808826990_0 .net "B", 0 0, L_0x56080883dbb0; alias, 1 drivers
|
||||||
|
v0x560808826a30_0 .net "Carry", 0 0, L_0x56080883d5b0; alias, 1 drivers
|
||||||
|
v0x560808826b00_0 .net "Sum", 0 0, L_0x56080883d700; alias, 1 drivers
|
||||||
|
S_0x560808827320 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608087fbca0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x56080883df50 .functor OR 1, L_0x56080883dce0, L_0x56080883ddc0, C4<0>, C4<0>;
|
||||||
|
v0x5608088280b0_0 .net "A", 0 0, L_0x56080883dfe0; 1 drivers
|
||||||
|
v0x560808828170_0 .net "B", 0 0, L_0x56080883e150; 1 drivers
|
||||||
|
v0x560808828240_0 .net "Carry", 0 0, L_0x56080883e280; 1 drivers
|
||||||
|
v0x560808828340_0 .net "CarryO", 0 0, L_0x56080883df50; 1 drivers
|
||||||
|
v0x5608088283e0_0 .net "Sum", 0 0, L_0x56080883dec0; 1 drivers
|
||||||
|
v0x5608088284d0_0 .net "and1", 0 0, L_0x56080883dce0; 1 drivers
|
||||||
|
v0x5608088285a0_0 .net "and2", 0 0, L_0x56080883ddc0; 1 drivers
|
||||||
|
v0x560808828670_0 .net "xor1", 0 0, L_0x56080883dd50; 1 drivers
|
||||||
|
S_0x560808827530 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808827320;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883dce0 .functor AND 1, L_0x56080883dfe0, L_0x56080883e150, C4<1>, C4<1>;
|
||||||
|
L_0x56080883dd50 .functor XOR 1, L_0x56080883dfe0, L_0x56080883e150, C4<0>, C4<0>;
|
||||||
|
v0x560808827740_0 .net "A", 0 0, L_0x56080883dfe0; alias, 1 drivers
|
||||||
|
v0x560808827800_0 .net "B", 0 0, L_0x56080883e150; alias, 1 drivers
|
||||||
|
v0x5608088278c0_0 .net "Carry", 0 0, L_0x56080883dce0; alias, 1 drivers
|
||||||
|
v0x560808827990_0 .net "Sum", 0 0, L_0x56080883dd50; alias, 1 drivers
|
||||||
|
S_0x560808827b00 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808827320;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883ddc0 .functor AND 1, L_0x56080883dd50, L_0x56080883e280, C4<1>, C4<1>;
|
||||||
|
L_0x56080883dec0 .functor XOR 1, L_0x56080883dd50, L_0x56080883e280, C4<0>, C4<0>;
|
||||||
|
v0x560808827d00_0 .net "A", 0 0, L_0x56080883dd50; alias, 1 drivers
|
||||||
|
v0x560808827dd0_0 .net "B", 0 0, L_0x56080883e280; alias, 1 drivers
|
||||||
|
v0x560808827e70_0 .net "Carry", 0 0, L_0x56080883ddc0; alias, 1 drivers
|
||||||
|
v0x560808827f40_0 .net "Sum", 0 0, L_0x56080883dec0; alias, 1 drivers
|
||||||
|
S_0x560808828760 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608087fbca0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x56080883e990 .functor OR 1, L_0x56080883e4f0, L_0x56080883e720, C4<0>, C4<0>;
|
||||||
|
v0x5608088294e0_0 .net "A", 0 0, L_0x56080883ea90; 1 drivers
|
||||||
|
v0x5608088295a0_0 .net "B", 0 0, L_0x56080883ec20; 1 drivers
|
||||||
|
v0x560808829670_0 .net "Carry", 0 0, L_0x56080883ed50; 1 drivers
|
||||||
|
v0x560808829770_0 .net "CarryO", 0 0, L_0x56080883e990; alias, 1 drivers
|
||||||
|
v0x560808829810_0 .net "Sum", 0 0, L_0x56080883e8b0; 1 drivers
|
||||||
|
v0x560808829900_0 .net "and1", 0 0, L_0x56080883e4f0; 1 drivers
|
||||||
|
v0x5608088299d0_0 .net "and2", 0 0, L_0x56080883e720; 1 drivers
|
||||||
|
v0x560808829aa0_0 .net "xor1", 0 0, L_0x56080883e690; 1 drivers
|
||||||
|
S_0x560808828940 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808828760;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883e4f0 .functor AND 1, L_0x56080883ea90, L_0x56080883ec20, C4<1>, C4<1>;
|
||||||
|
L_0x56080883e690 .functor XOR 1, L_0x56080883ea90, L_0x56080883ec20, C4<0>, C4<0>;
|
||||||
|
v0x560808828b50_0 .net "A", 0 0, L_0x56080883ea90; alias, 1 drivers
|
||||||
|
v0x560808828c30_0 .net "B", 0 0, L_0x56080883ec20; alias, 1 drivers
|
||||||
|
v0x560808828cf0_0 .net "Carry", 0 0, L_0x56080883e4f0; alias, 1 drivers
|
||||||
|
v0x560808828dc0_0 .net "Sum", 0 0, L_0x56080883e690; alias, 1 drivers
|
||||||
|
S_0x560808828f30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808828760;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x56080883e720 .functor AND 1, L_0x56080883e690, L_0x56080883ed50, C4<1>, C4<1>;
|
||||||
|
L_0x56080883e8b0 .functor XOR 1, L_0x56080883e690, L_0x56080883ed50, C4<0>, C4<0>;
|
||||||
|
v0x560808829130_0 .net "A", 0 0, L_0x56080883e690; alias, 1 drivers
|
||||||
|
v0x560808829200_0 .net "B", 0 0, L_0x56080883ed50; alias, 1 drivers
|
||||||
|
v0x5608088292a0_0 .net "Carry", 0 0, L_0x56080883e720; alias, 1 drivers
|
||||||
|
v0x560808829370_0 .net "Sum", 0 0, L_0x56080883e8b0; alias, 1 drivers
|
||||||
|
S_0x56080882a310 .scope module, "add1" "addition" 3 42, 4 1 0, S_0x560808804330;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 4 "A";
|
||||||
|
.port_info 1 /INPUT 4 "B";
|
||||||
|
.port_info 2 /INPUT 1 "CarryIN";
|
||||||
|
.port_info 3 /OUTPUT 4 "Y";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryOUT";
|
||||||
|
.port_info 5 /OUTPUT 1 "overflow";
|
||||||
|
L_0x5608088424e0 .functor XOR 1, L_0x560808842550, L_0x560808841dc0, C4<0>, C4<0>;
|
||||||
|
v0x56080882fa20_0 .net "A", 3 0, L_0x56080883fab0; alias, 1 drivers
|
||||||
|
v0x56080882fb00_0 .net "B", 3 0, L_0x560808842670; 1 drivers
|
||||||
|
v0x56080882fbe0_0 .net "Carry4", 2 0, L_0x560808841830; 1 drivers
|
||||||
|
L_0x7f3ea6b4d0a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
v0x56080882fca0_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0a8; 1 drivers
|
||||||
|
v0x56080882fd90_0 .net "CarryOUT", 0 0, L_0x560808841dc0; 1 drivers
|
||||||
|
v0x56080882fe80_0 .net "Y", 3 0, L_0x560808842440; 1 drivers
|
||||||
|
v0x56080882ff40_0 .net *"_ivl_39", 0 0, L_0x560808842550; 1 drivers
|
||||||
|
v0x560808830020_0 .net "overflow", 0 0, L_0x5608088424e0; alias, 1 drivers
|
||||||
|
L_0x560808840590 .part L_0x56080883fab0, 0, 1;
|
||||||
|
L_0x5608088406c0 .part L_0x560808842670, 0, 1;
|
||||||
|
L_0x560808840bf0 .part L_0x56080883fab0, 1, 1;
|
||||||
|
L_0x560808840db0 .part L_0x560808842670, 1, 1;
|
||||||
|
L_0x560808840ee0 .part L_0x560808841830, 0, 1;
|
||||||
|
L_0x560808841410 .part L_0x56080883fab0, 2, 1;
|
||||||
|
L_0x560808841580 .part L_0x560808842670, 2, 1;
|
||||||
|
L_0x5608088416b0 .part L_0x560808841830, 1, 1;
|
||||||
|
L_0x560808841830 .concat8 [ 1 1 1 0], L_0x560808840520, L_0x560808840b60, L_0x560808841380;
|
||||||
|
L_0x560808841ec0 .part L_0x56080883fab0, 3, 1;
|
||||||
|
L_0x560808842050 .part L_0x560808842670, 3, 1;
|
||||||
|
L_0x560808842210 .part L_0x560808841830, 2, 1;
|
||||||
|
L_0x560808842440 .concat8 [ 1 1 1 1], L_0x560808840420, L_0x560808840a80, L_0x5608088412a0, L_0x560808841ce0;
|
||||||
|
L_0x560808842550 .part L_0x560808841830, 2, 1;
|
||||||
|
S_0x56080882a5b0 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x56080882a310;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x560808840520 .functor OR 1, L_0x560808840100, L_0x5608088402d0, C4<0>, C4<0>;
|
||||||
|
v0x56080882b430_0 .net "A", 0 0, L_0x560808840590; 1 drivers
|
||||||
|
v0x56080882b4f0_0 .net "B", 0 0, L_0x5608088406c0; 1 drivers
|
||||||
|
v0x56080882b5c0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0a8; alias, 1 drivers
|
||||||
|
v0x56080882b6c0_0 .net "CarryO", 0 0, L_0x560808840520; 1 drivers
|
||||||
|
v0x56080882b760_0 .net "Sum", 0 0, L_0x560808840420; 1 drivers
|
||||||
|
v0x56080882b850_0 .net "and1", 0 0, L_0x560808840100; 1 drivers
|
||||||
|
v0x56080882b920_0 .net "and2", 0 0, L_0x5608088402d0; 1 drivers
|
||||||
|
v0x56080882b9f0_0 .net "xor1", 0 0, L_0x560808840260; 1 drivers
|
||||||
|
S_0x56080882a790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882a5b0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808840100 .functor AND 1, L_0x560808840590, L_0x5608088406c0, C4<1>, C4<1>;
|
||||||
|
L_0x560808840260 .functor XOR 1, L_0x560808840590, L_0x5608088406c0, C4<0>, C4<0>;
|
||||||
|
v0x56080882aa30_0 .net "A", 0 0, L_0x560808840590; alias, 1 drivers
|
||||||
|
v0x56080882ab10_0 .net "B", 0 0, L_0x5608088406c0; alias, 1 drivers
|
||||||
|
v0x56080882abd0_0 .net "Carry", 0 0, L_0x560808840100; alias, 1 drivers
|
||||||
|
v0x56080882aca0_0 .net "Sum", 0 0, L_0x560808840260; alias, 1 drivers
|
||||||
|
S_0x56080882ae10 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882a5b0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x5608088402d0 .functor AND 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<1>, C4<1>;
|
||||||
|
L_0x560808840420 .functor XOR 1, L_0x560808840260, L_0x7f3ea6b4d0a8, C4<0>, C4<0>;
|
||||||
|
v0x56080882b080_0 .net "A", 0 0, L_0x560808840260; alias, 1 drivers
|
||||||
|
v0x56080882b150_0 .net "B", 0 0, L_0x7f3ea6b4d0a8; alias, 1 drivers
|
||||||
|
v0x56080882b1f0_0 .net "Carry", 0 0, L_0x5608088402d0; alias, 1 drivers
|
||||||
|
v0x56080882b2c0_0 .net "Sum", 0 0, L_0x560808840420; alias, 1 drivers
|
||||||
|
S_0x56080882bae0 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x56080882a310;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x560808840b60 .functor OR 1, L_0x5608088407f0, L_0x5608088408f0, C4<0>, C4<0>;
|
||||||
|
v0x56080882c940_0 .net "A", 0 0, L_0x560808840bf0; 1 drivers
|
||||||
|
v0x56080882ca00_0 .net "B", 0 0, L_0x560808840db0; 1 drivers
|
||||||
|
v0x56080882cad0_0 .net "Carry", 0 0, L_0x560808840ee0; 1 drivers
|
||||||
|
v0x56080882cbd0_0 .net "CarryO", 0 0, L_0x560808840b60; 1 drivers
|
||||||
|
v0x56080882cc70_0 .net "Sum", 0 0, L_0x560808840a80; 1 drivers
|
||||||
|
v0x56080882cd60_0 .net "and1", 0 0, L_0x5608088407f0; 1 drivers
|
||||||
|
v0x56080882ce30_0 .net "and2", 0 0, L_0x5608088408f0; 1 drivers
|
||||||
|
v0x56080882cf00_0 .net "xor1", 0 0, L_0x560808840860; 1 drivers
|
||||||
|
S_0x56080882bcc0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882bae0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x5608088407f0 .functor AND 1, L_0x560808840bf0, L_0x560808840db0, C4<1>, C4<1>;
|
||||||
|
L_0x560808840860 .functor XOR 1, L_0x560808840bf0, L_0x560808840db0, C4<0>, C4<0>;
|
||||||
|
v0x56080882bf40_0 .net "A", 0 0, L_0x560808840bf0; alias, 1 drivers
|
||||||
|
v0x56080882c020_0 .net "B", 0 0, L_0x560808840db0; alias, 1 drivers
|
||||||
|
v0x56080882c0e0_0 .net "Carry", 0 0, L_0x5608088407f0; alias, 1 drivers
|
||||||
|
v0x56080882c1b0_0 .net "Sum", 0 0, L_0x560808840860; alias, 1 drivers
|
||||||
|
S_0x56080882c320 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882bae0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x5608088408f0 .functor AND 1, L_0x560808840860, L_0x560808840ee0, C4<1>, C4<1>;
|
||||||
|
L_0x560808840a80 .functor XOR 1, L_0x560808840860, L_0x560808840ee0, C4<0>, C4<0>;
|
||||||
|
v0x56080882c590_0 .net "A", 0 0, L_0x560808840860; alias, 1 drivers
|
||||||
|
v0x56080882c660_0 .net "B", 0 0, L_0x560808840ee0; alias, 1 drivers
|
||||||
|
v0x56080882c700_0 .net "Carry", 0 0, L_0x5608088408f0; alias, 1 drivers
|
||||||
|
v0x56080882c7d0_0 .net "Sum", 0 0, L_0x560808840a80; alias, 1 drivers
|
||||||
|
S_0x56080882cff0 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x56080882a310;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x560808841380 .functor OR 1, L_0x560808841010, L_0x560808841110, C4<0>, C4<0>;
|
||||||
|
v0x56080882de60_0 .net "A", 0 0, L_0x560808841410; 1 drivers
|
||||||
|
v0x56080882df20_0 .net "B", 0 0, L_0x560808841580; 1 drivers
|
||||||
|
v0x56080882dff0_0 .net "Carry", 0 0, L_0x5608088416b0; 1 drivers
|
||||||
|
v0x56080882e0f0_0 .net "CarryO", 0 0, L_0x560808841380; 1 drivers
|
||||||
|
v0x56080882e190_0 .net "Sum", 0 0, L_0x5608088412a0; 1 drivers
|
||||||
|
v0x56080882e280_0 .net "and1", 0 0, L_0x560808841010; 1 drivers
|
||||||
|
v0x56080882e350_0 .net "and2", 0 0, L_0x560808841110; 1 drivers
|
||||||
|
v0x56080882e420_0 .net "xor1", 0 0, L_0x560808841080; 1 drivers
|
||||||
|
S_0x56080882d200 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882cff0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808841010 .functor AND 1, L_0x560808841410, L_0x560808841580, C4<1>, C4<1>;
|
||||||
|
L_0x560808841080 .functor XOR 1, L_0x560808841410, L_0x560808841580, C4<0>, C4<0>;
|
||||||
|
v0x56080882d480_0 .net "A", 0 0, L_0x560808841410; alias, 1 drivers
|
||||||
|
v0x56080882d540_0 .net "B", 0 0, L_0x560808841580; alias, 1 drivers
|
||||||
|
v0x56080882d600_0 .net "Carry", 0 0, L_0x560808841010; alias, 1 drivers
|
||||||
|
v0x56080882d6d0_0 .net "Sum", 0 0, L_0x560808841080; alias, 1 drivers
|
||||||
|
S_0x56080882d840 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882cff0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808841110 .functor AND 1, L_0x560808841080, L_0x5608088416b0, C4<1>, C4<1>;
|
||||||
|
L_0x5608088412a0 .functor XOR 1, L_0x560808841080, L_0x5608088416b0, C4<0>, C4<0>;
|
||||||
|
v0x56080882dab0_0 .net "A", 0 0, L_0x560808841080; alias, 1 drivers
|
||||||
|
v0x56080882db80_0 .net "B", 0 0, L_0x5608088416b0; alias, 1 drivers
|
||||||
|
v0x56080882dc20_0 .net "Carry", 0 0, L_0x560808841110; alias, 1 drivers
|
||||||
|
v0x56080882dcf0_0 .net "Sum", 0 0, L_0x5608088412a0; alias, 1 drivers
|
||||||
|
S_0x56080882e510 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x56080882a310;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x560808841dc0 .functor OR 1, L_0x560808841920, L_0x560808841b50, C4<0>, C4<0>;
|
||||||
|
v0x56080882f370_0 .net "A", 0 0, L_0x560808841ec0; 1 drivers
|
||||||
|
v0x56080882f430_0 .net "B", 0 0, L_0x560808842050; 1 drivers
|
||||||
|
v0x56080882f500_0 .net "Carry", 0 0, L_0x560808842210; 1 drivers
|
||||||
|
v0x56080882f600_0 .net "CarryO", 0 0, L_0x560808841dc0; alias, 1 drivers
|
||||||
|
v0x56080882f6a0_0 .net "Sum", 0 0, L_0x560808841ce0; 1 drivers
|
||||||
|
v0x56080882f790_0 .net "and1", 0 0, L_0x560808841920; 1 drivers
|
||||||
|
v0x56080882f860_0 .net "and2", 0 0, L_0x560808841b50; 1 drivers
|
||||||
|
v0x56080882f930_0 .net "xor1", 0 0, L_0x560808841ac0; 1 drivers
|
||||||
|
S_0x56080882e6f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x56080882e510;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808841920 .functor AND 1, L_0x560808841ec0, L_0x560808842050, C4<1>, C4<1>;
|
||||||
|
L_0x560808841ac0 .functor XOR 1, L_0x560808841ec0, L_0x560808842050, C4<0>, C4<0>;
|
||||||
|
v0x56080882e970_0 .net "A", 0 0, L_0x560808841ec0; alias, 1 drivers
|
||||||
|
v0x56080882ea50_0 .net "B", 0 0, L_0x560808842050; alias, 1 drivers
|
||||||
|
v0x56080882eb10_0 .net "Carry", 0 0, L_0x560808841920; alias, 1 drivers
|
||||||
|
v0x56080882ebe0_0 .net "Sum", 0 0, L_0x560808841ac0; alias, 1 drivers
|
||||||
|
S_0x56080882ed50 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x56080882e510;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808841b50 .functor AND 1, L_0x560808841ac0, L_0x560808842210, C4<1>, C4<1>;
|
||||||
|
L_0x560808841ce0 .functor XOR 1, L_0x560808841ac0, L_0x560808842210, C4<0>, C4<0>;
|
||||||
|
v0x56080882efc0_0 .net "A", 0 0, L_0x560808841ac0; alias, 1 drivers
|
||||||
|
v0x56080882f090_0 .net "B", 0 0, L_0x560808842210; alias, 1 drivers
|
||||||
|
v0x56080882f130_0 .net "Carry", 0 0, L_0x560808841b50; alias, 1 drivers
|
||||||
|
v0x56080882f200_0 .net "Sum", 0 0, L_0x560808841ce0; alias, 1 drivers
|
||||||
|
S_0x5608088301a0 .scope module, "add2" "addition" 3 58, 4 1 0, S_0x560808804330;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 4 "A";
|
||||||
|
.port_info 1 /INPUT 4 "B";
|
||||||
|
.port_info 2 /INPUT 1 "CarryIN";
|
||||||
|
.port_info 3 /OUTPUT 4 "Y";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryOUT";
|
||||||
|
.port_info 5 /OUTPUT 1 "overflow";
|
||||||
|
L_0x560808845a10 .functor XOR 1, L_0x560808845a80, L_0x560808845330, C4<0>, C4<0>;
|
||||||
|
v0x560808835ac0_0 .net "A", 3 0, L_0x560808842da0; alias, 1 drivers
|
||||||
|
v0x560808835ba0_0 .net "B", 3 0, L_0x560808845ba0; 1 drivers
|
||||||
|
v0x560808835c80_0 .net "Carry4", 2 0, L_0x560808844e60; 1 drivers
|
||||||
|
L_0x7f3ea6b4d0f0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
v0x560808835d40_0 .net "CarryIN", 0 0, L_0x7f3ea6b4d0f0; 1 drivers
|
||||||
|
v0x560808835e30_0 .net "CarryOUT", 0 0, L_0x560808845330; 1 drivers
|
||||||
|
v0x560808835f20_0 .net "Y", 3 0, L_0x560808845970; 1 drivers
|
||||||
|
v0x560808835fe0_0 .net *"_ivl_39", 0 0, L_0x560808845a80; 1 drivers
|
||||||
|
v0x5608088360c0_0 .net "overflow", 0 0, L_0x560808845a10; alias, 1 drivers
|
||||||
|
L_0x560808843e40 .part L_0x560808842da0, 0, 1;
|
||||||
|
L_0x560808843f70 .part L_0x560808845ba0, 0, 1;
|
||||||
|
L_0x560808844360 .part L_0x560808842da0, 1, 1;
|
||||||
|
L_0x560808844520 .part L_0x560808845ba0, 1, 1;
|
||||||
|
L_0x560808844650 .part L_0x560808844e60, 0, 1;
|
||||||
|
L_0x560808844a40 .part L_0x560808842da0, 2, 1;
|
||||||
|
L_0x560808844bb0 .part L_0x560808845ba0, 2, 1;
|
||||||
|
L_0x560808844ce0 .part L_0x560808844e60, 1, 1;
|
||||||
|
L_0x560808844e60 .concat8 [ 1 1 1 0], L_0x560808843dd0, L_0x5608088442f0, L_0x5608088449d0;
|
||||||
|
L_0x5608088453f0 .part L_0x560808842da0, 3, 1;
|
||||||
|
L_0x560808845580 .part L_0x560808845ba0, 3, 1;
|
||||||
|
L_0x560808845740 .part L_0x560808844e60, 2, 1;
|
||||||
|
L_0x560808845970 .concat8 [ 1 1 1 1], L_0x560808843cd0, L_0x560808844280, L_0x560808844960, L_0x560808845270;
|
||||||
|
L_0x560808845a80 .part L_0x560808844e60, 2, 1;
|
||||||
|
S_0x560808830420 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x5608088301a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x560808843dd0 .functor OR 1, L_0x5608088439b0, L_0x560808843b80, C4<0>, C4<0>;
|
||||||
|
v0x560808831350_0 .net "A", 0 0, L_0x560808843e40; 1 drivers
|
||||||
|
v0x560808831410_0 .net "B", 0 0, L_0x560808843f70; 1 drivers
|
||||||
|
v0x5608088314e0_0 .net "Carry", 0 0, L_0x7f3ea6b4d0f0; alias, 1 drivers
|
||||||
|
v0x5608088315e0_0 .net "CarryO", 0 0, L_0x560808843dd0; 1 drivers
|
||||||
|
v0x560808831680_0 .net "Sum", 0 0, L_0x560808843cd0; 1 drivers
|
||||||
|
v0x560808831770_0 .net "and1", 0 0, L_0x5608088439b0; 1 drivers
|
||||||
|
v0x560808831840_0 .net "and2", 0 0, L_0x560808843b80; 1 drivers
|
||||||
|
v0x560808831910_0 .net "xor1", 0 0, L_0x560808843b10; 1 drivers
|
||||||
|
S_0x5608088306b0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808830420;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x5608088439b0 .functor AND 1, L_0x560808843e40, L_0x560808843f70, C4<1>, C4<1>;
|
||||||
|
L_0x560808843b10 .functor XOR 1, L_0x560808843e40, L_0x560808843f70, C4<0>, C4<0>;
|
||||||
|
v0x560808830950_0 .net "A", 0 0, L_0x560808843e40; alias, 1 drivers
|
||||||
|
v0x560808830a30_0 .net "B", 0 0, L_0x560808843f70; alias, 1 drivers
|
||||||
|
v0x560808830af0_0 .net "Carry", 0 0, L_0x5608088439b0; alias, 1 drivers
|
||||||
|
v0x560808830bc0_0 .net "Sum", 0 0, L_0x560808843b10; alias, 1 drivers
|
||||||
|
S_0x560808830d30 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808830420;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808843b80 .functor AND 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<1>, C4<1>;
|
||||||
|
L_0x560808843cd0 .functor XOR 1, L_0x560808843b10, L_0x7f3ea6b4d0f0, C4<0>, C4<0>;
|
||||||
|
v0x560808830fa0_0 .net "A", 0 0, L_0x560808843b10; alias, 1 drivers
|
||||||
|
v0x560808831070_0 .net "B", 0 0, L_0x7f3ea6b4d0f0; alias, 1 drivers
|
||||||
|
v0x560808831110_0 .net "Carry", 0 0, L_0x560808843b80; alias, 1 drivers
|
||||||
|
v0x5608088311e0_0 .net "Sum", 0 0, L_0x560808843cd0; alias, 1 drivers
|
||||||
|
S_0x560808831a00 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x5608088301a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x5608088442f0 .functor OR 1, L_0x5608088440a0, L_0x560808844180, C4<0>, C4<0>;
|
||||||
|
v0x5608088328e0_0 .net "A", 0 0, L_0x560808844360; 1 drivers
|
||||||
|
v0x5608088329a0_0 .net "B", 0 0, L_0x560808844520; 1 drivers
|
||||||
|
v0x560808832a70_0 .net "Carry", 0 0, L_0x560808844650; 1 drivers
|
||||||
|
v0x560808832b70_0 .net "CarryO", 0 0, L_0x5608088442f0; 1 drivers
|
||||||
|
v0x560808832c10_0 .net "Sum", 0 0, L_0x560808844280; 1 drivers
|
||||||
|
v0x560808832d00_0 .net "and1", 0 0, L_0x5608088440a0; 1 drivers
|
||||||
|
v0x560808832dd0_0 .net "and2", 0 0, L_0x560808844180; 1 drivers
|
||||||
|
v0x560808832ea0_0 .net "xor1", 0 0, L_0x560808844110; 1 drivers
|
||||||
|
S_0x560808831c60 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808831a00;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x5608088440a0 .functor AND 1, L_0x560808844360, L_0x560808844520, C4<1>, C4<1>;
|
||||||
|
L_0x560808844110 .functor XOR 1, L_0x560808844360, L_0x560808844520, C4<0>, C4<0>;
|
||||||
|
v0x560808831ee0_0 .net "A", 0 0, L_0x560808844360; alias, 1 drivers
|
||||||
|
v0x560808831fc0_0 .net "B", 0 0, L_0x560808844520; alias, 1 drivers
|
||||||
|
v0x560808832080_0 .net "Carry", 0 0, L_0x5608088440a0; alias, 1 drivers
|
||||||
|
v0x560808832150_0 .net "Sum", 0 0, L_0x560808844110; alias, 1 drivers
|
||||||
|
S_0x5608088322c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808831a00;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808844180 .functor AND 1, L_0x560808844110, L_0x560808844650, C4<1>, C4<1>;
|
||||||
|
L_0x560808844280 .functor XOR 1, L_0x560808844110, L_0x560808844650, C4<0>, C4<0>;
|
||||||
|
v0x560808832530_0 .net "A", 0 0, L_0x560808844110; alias, 1 drivers
|
||||||
|
v0x560808832600_0 .net "B", 0 0, L_0x560808844650; alias, 1 drivers
|
||||||
|
v0x5608088326a0_0 .net "Carry", 0 0, L_0x560808844180; alias, 1 drivers
|
||||||
|
v0x560808832770_0 .net "Sum", 0 0, L_0x560808844280; alias, 1 drivers
|
||||||
|
S_0x560808832f90 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x5608088301a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x5608088449d0 .functor OR 1, L_0x560808844780, L_0x560808844860, C4<0>, C4<0>;
|
||||||
|
v0x560808833e80_0 .net "A", 0 0, L_0x560808844a40; 1 drivers
|
||||||
|
v0x560808833f40_0 .net "B", 0 0, L_0x560808844bb0; 1 drivers
|
||||||
|
v0x560808834010_0 .net "Carry", 0 0, L_0x560808844ce0; 1 drivers
|
||||||
|
v0x560808834110_0 .net "CarryO", 0 0, L_0x5608088449d0; 1 drivers
|
||||||
|
v0x5608088341b0_0 .net "Sum", 0 0, L_0x560808844960; 1 drivers
|
||||||
|
v0x5608088342a0_0 .net "and1", 0 0, L_0x560808844780; 1 drivers
|
||||||
|
v0x560808834370_0 .net "and2", 0 0, L_0x560808844860; 1 drivers
|
||||||
|
v0x560808834440_0 .net "xor1", 0 0, L_0x5608088447f0; 1 drivers
|
||||||
|
S_0x560808833220 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808832f90;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808844780 .functor AND 1, L_0x560808844a40, L_0x560808844bb0, C4<1>, C4<1>;
|
||||||
|
L_0x5608088447f0 .functor XOR 1, L_0x560808844a40, L_0x560808844bb0, C4<0>, C4<0>;
|
||||||
|
v0x5608088334a0_0 .net "A", 0 0, L_0x560808844a40; alias, 1 drivers
|
||||||
|
v0x560808833560_0 .net "B", 0 0, L_0x560808844bb0; alias, 1 drivers
|
||||||
|
v0x560808833620_0 .net "Carry", 0 0, L_0x560808844780; alias, 1 drivers
|
||||||
|
v0x5608088336f0_0 .net "Sum", 0 0, L_0x5608088447f0; alias, 1 drivers
|
||||||
|
S_0x560808833860 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808832f90;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808844860 .functor AND 1, L_0x5608088447f0, L_0x560808844ce0, C4<1>, C4<1>;
|
||||||
|
L_0x560808844960 .functor XOR 1, L_0x5608088447f0, L_0x560808844ce0, C4<0>, C4<0>;
|
||||||
|
v0x560808833ad0_0 .net "A", 0 0, L_0x5608088447f0; alias, 1 drivers
|
||||||
|
v0x560808833ba0_0 .net "B", 0 0, L_0x560808844ce0; alias, 1 drivers
|
||||||
|
v0x560808833c40_0 .net "Carry", 0 0, L_0x560808844860; alias, 1 drivers
|
||||||
|
v0x560808833d10_0 .net "Sum", 0 0, L_0x560808844960; alias, 1 drivers
|
||||||
|
S_0x560808834530 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x5608088301a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x560808845330 .functor OR 1, L_0x560808844f50, L_0x560808845120, C4<0>, C4<0>;
|
||||||
|
v0x560808835410_0 .net "A", 0 0, L_0x5608088453f0; 1 drivers
|
||||||
|
v0x5608088354d0_0 .net "B", 0 0, L_0x560808845580; 1 drivers
|
||||||
|
v0x5608088355a0_0 .net "Carry", 0 0, L_0x560808845740; 1 drivers
|
||||||
|
v0x5608088356a0_0 .net "CarryO", 0 0, L_0x560808845330; alias, 1 drivers
|
||||||
|
v0x560808835740_0 .net "Sum", 0 0, L_0x560808845270; 1 drivers
|
||||||
|
v0x560808835830_0 .net "and1", 0 0, L_0x560808844f50; 1 drivers
|
||||||
|
v0x560808835900_0 .net "and2", 0 0, L_0x560808845120; 1 drivers
|
||||||
|
v0x5608088359d0_0 .net "xor1", 0 0, L_0x5608088450b0; 1 drivers
|
||||||
|
S_0x560808834790 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x560808834530;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808844f50 .functor AND 1, L_0x5608088453f0, L_0x560808845580, C4<1>, C4<1>;
|
||||||
|
L_0x5608088450b0 .functor XOR 1, L_0x5608088453f0, L_0x560808845580, C4<0>, C4<0>;
|
||||||
|
v0x560808834a10_0 .net "A", 0 0, L_0x5608088453f0; alias, 1 drivers
|
||||||
|
v0x560808834af0_0 .net "B", 0 0, L_0x560808845580; alias, 1 drivers
|
||||||
|
v0x560808834bb0_0 .net "Carry", 0 0, L_0x560808844f50; alias, 1 drivers
|
||||||
|
v0x560808834c80_0 .net "Sum", 0 0, L_0x5608088450b0; alias, 1 drivers
|
||||||
|
S_0x560808834df0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x560808834530;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x560808845120 .functor AND 1, L_0x5608088450b0, L_0x560808845740, C4<1>, C4<1>;
|
||||||
|
L_0x560808845270 .functor XOR 1, L_0x5608088450b0, L_0x560808845740, C4<0>, C4<0>;
|
||||||
|
v0x560808835060_0 .net "A", 0 0, L_0x5608088450b0; alias, 1 drivers
|
||||||
|
v0x560808835130_0 .net "B", 0 0, L_0x560808845740; alias, 1 drivers
|
||||||
|
v0x5608088351d0_0 .net "Carry", 0 0, L_0x560808845120; alias, 1 drivers
|
||||||
|
v0x5608088352a0_0 .net "Sum", 0 0, L_0x560808845270; alias, 1 drivers
|
||||||
|
.scope S_0x560808805dd0;
|
||||||
|
T_0 ;
|
||||||
|
%vpi_call 2 13 "$dumpfile", "mult.vcd" {0 0 0};
|
||||||
|
%vpi_call 2 14 "$dumpvars" {0 0 0};
|
||||||
|
%pushi/vec4 8, 0, 4;
|
||||||
|
%store/vec4 v0x56080883b1b0_0, 0, 4;
|
||||||
|
%pushi/vec4 8, 0, 4;
|
||||||
|
%store/vec4 v0x56080883b2a0_0, 0, 4;
|
||||||
|
%delay 5, 0;
|
||||||
|
%end;
|
||||||
|
.thread T_0;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 7;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"multTB.v";
|
||||||
|
"multiplier.v";
|
||||||
|
"addition.v";
|
||||||
|
"fulladder.v";
|
||||||
|
"halfadder.v";
|
449
tangTest/mult.vcd
Normal file
449
tangTest/mult.vcd
Normal file
@ -0,0 +1,449 @@
|
|||||||
|
$date
|
||||||
|
Sun Jan 19 14:35:11 2025
|
||||||
|
$end
|
||||||
|
$version
|
||||||
|
Icarus Verilog
|
||||||
|
$end
|
||||||
|
$timescale
|
||||||
|
1s
|
||||||
|
$end
|
||||||
|
$scope module multTB $end
|
||||||
|
$var wire 8 ! Y [7:0] $end
|
||||||
|
$var reg 4 " A [3:0] $end
|
||||||
|
$var reg 4 # B [3:0] $end
|
||||||
|
$scope module uut $end
|
||||||
|
$var wire 4 $ A [3:0] $end
|
||||||
|
$var wire 4 % B [3:0] $end
|
||||||
|
$var wire 1 & overflow2 $end
|
||||||
|
$var wire 1 ' overflow1 $end
|
||||||
|
$var wire 1 ( overflow0 $end
|
||||||
|
$var wire 4 ) b0 [3:0] $end
|
||||||
|
$var wire 4 * a2 [3:0] $end
|
||||||
|
$var wire 4 + a1 [3:0] $end
|
||||||
|
$var wire 4 , a0 [3:0] $end
|
||||||
|
$var wire 8 - Y [7:0] $end
|
||||||
|
$var wire 5 . S2 [4:0] $end
|
||||||
|
$var wire 5 / S1 [4:0] $end
|
||||||
|
$var wire 5 0 S0 [4:0] $end
|
||||||
|
$scope module add0 $end
|
||||||
|
$var wire 4 1 A [3:0] $end
|
||||||
|
$var wire 4 2 B [3:0] $end
|
||||||
|
$var wire 1 3 CarryIN $end
|
||||||
|
$var wire 1 ( overflow $end
|
||||||
|
$var wire 4 4 Y [3:0] $end
|
||||||
|
$var wire 1 5 CarryOUT $end
|
||||||
|
$var wire 3 6 Carry4 [2:0] $end
|
||||||
|
$scope module f0 $end
|
||||||
|
$var wire 1 7 A $end
|
||||||
|
$var wire 1 8 B $end
|
||||||
|
$var wire 1 3 Carry $end
|
||||||
|
$var wire 1 9 CarryO $end
|
||||||
|
$var wire 1 : xor1 $end
|
||||||
|
$var wire 1 ; and2 $end
|
||||||
|
$var wire 1 < and1 $end
|
||||||
|
$var wire 1 = Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 7 A $end
|
||||||
|
$var wire 1 8 B $end
|
||||||
|
$var wire 1 < Carry $end
|
||||||
|
$var wire 1 : Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 : A $end
|
||||||
|
$var wire 1 3 B $end
|
||||||
|
$var wire 1 ; Carry $end
|
||||||
|
$var wire 1 = Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 > A $end
|
||||||
|
$var wire 1 ? B $end
|
||||||
|
$var wire 1 @ Carry $end
|
||||||
|
$var wire 1 A CarryO $end
|
||||||
|
$var wire 1 B xor1 $end
|
||||||
|
$var wire 1 C and2 $end
|
||||||
|
$var wire 1 D and1 $end
|
||||||
|
$var wire 1 E Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 > A $end
|
||||||
|
$var wire 1 ? B $end
|
||||||
|
$var wire 1 D Carry $end
|
||||||
|
$var wire 1 B Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 B A $end
|
||||||
|
$var wire 1 @ B $end
|
||||||
|
$var wire 1 C Carry $end
|
||||||
|
$var wire 1 E Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f2 $end
|
||||||
|
$var wire 1 F A $end
|
||||||
|
$var wire 1 G B $end
|
||||||
|
$var wire 1 H Carry $end
|
||||||
|
$var wire 1 I CarryO $end
|
||||||
|
$var wire 1 J xor1 $end
|
||||||
|
$var wire 1 K and2 $end
|
||||||
|
$var wire 1 L and1 $end
|
||||||
|
$var wire 1 M Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 F A $end
|
||||||
|
$var wire 1 G B $end
|
||||||
|
$var wire 1 L Carry $end
|
||||||
|
$var wire 1 J Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 J A $end
|
||||||
|
$var wire 1 H B $end
|
||||||
|
$var wire 1 K Carry $end
|
||||||
|
$var wire 1 M Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f3 $end
|
||||||
|
$var wire 1 N A $end
|
||||||
|
$var wire 1 O B $end
|
||||||
|
$var wire 1 P Carry $end
|
||||||
|
$var wire 1 5 CarryO $end
|
||||||
|
$var wire 1 Q xor1 $end
|
||||||
|
$var wire 1 R and2 $end
|
||||||
|
$var wire 1 S and1 $end
|
||||||
|
$var wire 1 T Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 N A $end
|
||||||
|
$var wire 1 O B $end
|
||||||
|
$var wire 1 S Carry $end
|
||||||
|
$var wire 1 Q Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 Q A $end
|
||||||
|
$var wire 1 P B $end
|
||||||
|
$var wire 1 R Carry $end
|
||||||
|
$var wire 1 T Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module add1 $end
|
||||||
|
$var wire 4 U A [3:0] $end
|
||||||
|
$var wire 4 V B [3:0] $end
|
||||||
|
$var wire 1 W CarryIN $end
|
||||||
|
$var wire 1 ' overflow $end
|
||||||
|
$var wire 4 X Y [3:0] $end
|
||||||
|
$var wire 1 Y CarryOUT $end
|
||||||
|
$var wire 3 Z Carry4 [2:0] $end
|
||||||
|
$scope module f0 $end
|
||||||
|
$var wire 1 [ A $end
|
||||||
|
$var wire 1 \ B $end
|
||||||
|
$var wire 1 W Carry $end
|
||||||
|
$var wire 1 ] CarryO $end
|
||||||
|
$var wire 1 ^ xor1 $end
|
||||||
|
$var wire 1 _ and2 $end
|
||||||
|
$var wire 1 ` and1 $end
|
||||||
|
$var wire 1 a Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 [ A $end
|
||||||
|
$var wire 1 \ B $end
|
||||||
|
$var wire 1 ` Carry $end
|
||||||
|
$var wire 1 ^ Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 ^ A $end
|
||||||
|
$var wire 1 W B $end
|
||||||
|
$var wire 1 _ Carry $end
|
||||||
|
$var wire 1 a Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 b A $end
|
||||||
|
$var wire 1 c B $end
|
||||||
|
$var wire 1 d Carry $end
|
||||||
|
$var wire 1 e CarryO $end
|
||||||
|
$var wire 1 f xor1 $end
|
||||||
|
$var wire 1 g and2 $end
|
||||||
|
$var wire 1 h and1 $end
|
||||||
|
$var wire 1 i Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 b A $end
|
||||||
|
$var wire 1 c B $end
|
||||||
|
$var wire 1 h Carry $end
|
||||||
|
$var wire 1 f Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 f A $end
|
||||||
|
$var wire 1 d B $end
|
||||||
|
$var wire 1 g Carry $end
|
||||||
|
$var wire 1 i Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f2 $end
|
||||||
|
$var wire 1 j A $end
|
||||||
|
$var wire 1 k B $end
|
||||||
|
$var wire 1 l Carry $end
|
||||||
|
$var wire 1 m CarryO $end
|
||||||
|
$var wire 1 n xor1 $end
|
||||||
|
$var wire 1 o and2 $end
|
||||||
|
$var wire 1 p and1 $end
|
||||||
|
$var wire 1 q Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 j A $end
|
||||||
|
$var wire 1 k B $end
|
||||||
|
$var wire 1 p Carry $end
|
||||||
|
$var wire 1 n Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 n A $end
|
||||||
|
$var wire 1 l B $end
|
||||||
|
$var wire 1 o Carry $end
|
||||||
|
$var wire 1 q Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f3 $end
|
||||||
|
$var wire 1 r A $end
|
||||||
|
$var wire 1 s B $end
|
||||||
|
$var wire 1 t Carry $end
|
||||||
|
$var wire 1 Y CarryO $end
|
||||||
|
$var wire 1 u xor1 $end
|
||||||
|
$var wire 1 v and2 $end
|
||||||
|
$var wire 1 w and1 $end
|
||||||
|
$var wire 1 x Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 r A $end
|
||||||
|
$var wire 1 s B $end
|
||||||
|
$var wire 1 w Carry $end
|
||||||
|
$var wire 1 u Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 u A $end
|
||||||
|
$var wire 1 t B $end
|
||||||
|
$var wire 1 v Carry $end
|
||||||
|
$var wire 1 x Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module add2 $end
|
||||||
|
$var wire 4 y A [3:0] $end
|
||||||
|
$var wire 4 z B [3:0] $end
|
||||||
|
$var wire 1 { CarryIN $end
|
||||||
|
$var wire 1 & overflow $end
|
||||||
|
$var wire 4 | Y [3:0] $end
|
||||||
|
$var wire 1 } CarryOUT $end
|
||||||
|
$var wire 3 ~ Carry4 [2:0] $end
|
||||||
|
$scope module f0 $end
|
||||||
|
$var wire 1 !" A $end
|
||||||
|
$var wire 1 "" B $end
|
||||||
|
$var wire 1 { Carry $end
|
||||||
|
$var wire 1 #" CarryO $end
|
||||||
|
$var wire 1 $" xor1 $end
|
||||||
|
$var wire 1 %" and2 $end
|
||||||
|
$var wire 1 &" and1 $end
|
||||||
|
$var wire 1 '" Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 !" A $end
|
||||||
|
$var wire 1 "" B $end
|
||||||
|
$var wire 1 &" Carry $end
|
||||||
|
$var wire 1 $" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 $" A $end
|
||||||
|
$var wire 1 { B $end
|
||||||
|
$var wire 1 %" Carry $end
|
||||||
|
$var wire 1 '" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 (" A $end
|
||||||
|
$var wire 1 )" B $end
|
||||||
|
$var wire 1 *" Carry $end
|
||||||
|
$var wire 1 +" CarryO $end
|
||||||
|
$var wire 1 ," xor1 $end
|
||||||
|
$var wire 1 -" and2 $end
|
||||||
|
$var wire 1 ." and1 $end
|
||||||
|
$var wire 1 /" Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 (" A $end
|
||||||
|
$var wire 1 )" B $end
|
||||||
|
$var wire 1 ." Carry $end
|
||||||
|
$var wire 1 ," Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 ," A $end
|
||||||
|
$var wire 1 *" B $end
|
||||||
|
$var wire 1 -" Carry $end
|
||||||
|
$var wire 1 /" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f2 $end
|
||||||
|
$var wire 1 0" A $end
|
||||||
|
$var wire 1 1" B $end
|
||||||
|
$var wire 1 2" Carry $end
|
||||||
|
$var wire 1 3" CarryO $end
|
||||||
|
$var wire 1 4" xor1 $end
|
||||||
|
$var wire 1 5" and2 $end
|
||||||
|
$var wire 1 6" and1 $end
|
||||||
|
$var wire 1 7" Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 0" A $end
|
||||||
|
$var wire 1 1" B $end
|
||||||
|
$var wire 1 6" Carry $end
|
||||||
|
$var wire 1 4" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 4" A $end
|
||||||
|
$var wire 1 2" B $end
|
||||||
|
$var wire 1 5" Carry $end
|
||||||
|
$var wire 1 7" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module f3 $end
|
||||||
|
$var wire 1 8" A $end
|
||||||
|
$var wire 1 9" B $end
|
||||||
|
$var wire 1 :" Carry $end
|
||||||
|
$var wire 1 } CarryO $end
|
||||||
|
$var wire 1 ;" xor1 $end
|
||||||
|
$var wire 1 <" and2 $end
|
||||||
|
$var wire 1 =" and1 $end
|
||||||
|
$var wire 1 >" Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 8" A $end
|
||||||
|
$var wire 1 9" B $end
|
||||||
|
$var wire 1 =" Carry $end
|
||||||
|
$var wire 1 ;" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 ;" A $end
|
||||||
|
$var wire 1 :" B $end
|
||||||
|
$var wire 1 <" Carry $end
|
||||||
|
$var wire 1 >" Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$enddefinitions $end
|
||||||
|
#0
|
||||||
|
$dumpvars
|
||||||
|
1>"
|
||||||
|
0="
|
||||||
|
0<"
|
||||||
|
1;"
|
||||||
|
0:"
|
||||||
|
09"
|
||||||
|
18"
|
||||||
|
07"
|
||||||
|
06"
|
||||||
|
05"
|
||||||
|
04"
|
||||||
|
03"
|
||||||
|
02"
|
||||||
|
01"
|
||||||
|
00"
|
||||||
|
0/"
|
||||||
|
0."
|
||||||
|
0-"
|
||||||
|
0,"
|
||||||
|
0+"
|
||||||
|
0*"
|
||||||
|
0)"
|
||||||
|
0("
|
||||||
|
0'"
|
||||||
|
0&"
|
||||||
|
0%"
|
||||||
|
0$"
|
||||||
|
0#"
|
||||||
|
0""
|
||||||
|
0!"
|
||||||
|
b0 ~
|
||||||
|
0}
|
||||||
|
b1000 |
|
||||||
|
0{
|
||||||
|
b0 z
|
||||||
|
b1000 y
|
||||||
|
0x
|
||||||
|
0w
|
||||||
|
0v
|
||||||
|
0u
|
||||||
|
0t
|
||||||
|
0s
|
||||||
|
0r
|
||||||
|
0q
|
||||||
|
0p
|
||||||
|
0o
|
||||||
|
0n
|
||||||
|
0m
|
||||||
|
0l
|
||||||
|
0k
|
||||||
|
0j
|
||||||
|
0i
|
||||||
|
0h
|
||||||
|
0g
|
||||||
|
0f
|
||||||
|
0e
|
||||||
|
0d
|
||||||
|
0c
|
||||||
|
0b
|
||||||
|
0a
|
||||||
|
0`
|
||||||
|
0_
|
||||||
|
0^
|
||||||
|
0]
|
||||||
|
0\
|
||||||
|
0[
|
||||||
|
b0 Z
|
||||||
|
0Y
|
||||||
|
b0 X
|
||||||
|
0W
|
||||||
|
b0 V
|
||||||
|
b0 U
|
||||||
|
0T
|
||||||
|
0S
|
||||||
|
0R
|
||||||
|
0Q
|
||||||
|
0P
|
||||||
|
0O
|
||||||
|
0N
|
||||||
|
0M
|
||||||
|
0L
|
||||||
|
0K
|
||||||
|
0J
|
||||||
|
0I
|
||||||
|
0H
|
||||||
|
0G
|
||||||
|
0F
|
||||||
|
0E
|
||||||
|
0D
|
||||||
|
0C
|
||||||
|
0B
|
||||||
|
0A
|
||||||
|
0@
|
||||||
|
0?
|
||||||
|
0>
|
||||||
|
0=
|
||||||
|
0<
|
||||||
|
0;
|
||||||
|
0:
|
||||||
|
09
|
||||||
|
08
|
||||||
|
07
|
||||||
|
b0 6
|
||||||
|
05
|
||||||
|
b0 4
|
||||||
|
03
|
||||||
|
b0 2
|
||||||
|
b0 1
|
||||||
|
b0 0
|
||||||
|
b0 /
|
||||||
|
b1000 .
|
||||||
|
b1000000 -
|
||||||
|
b0 ,
|
||||||
|
b0 +
|
||||||
|
b1000 *
|
||||||
|
b0 )
|
||||||
|
0(
|
||||||
|
0'
|
||||||
|
0&
|
||||||
|
b1000 %
|
||||||
|
b1000 $
|
||||||
|
b1000 #
|
||||||
|
b1000 "
|
||||||
|
b1000000 !
|
||||||
|
$end
|
||||||
|
#5
|
18
tangTest/multTB.v
Normal file
18
tangTest/multTB.v
Normal file
@ -0,0 +1,18 @@
|
|||||||
|
module multTB();
|
||||||
|
|
||||||
|
reg [3:0] A, B;
|
||||||
|
wire [7:0] Y;
|
||||||
|
|
||||||
|
multiplier uut (
|
||||||
|
.A(A),
|
||||||
|
.B(B),
|
||||||
|
.Y(Y)
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$dumpfile("mult.vcd");
|
||||||
|
$dumpvars;
|
||||||
|
A = 4'b1000; B = 4'b1000; #5;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
Loading…
x
Reference in New Issue
Block a user