29 lines
662 B
Verilog
29 lines
662 B
Verilog
module selectorTB();
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reg [1:0] select;
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reg [3:0] A, B;
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reg [7:0] ALUY;
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reg [2:0] opCodeA;
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wire [7:0] Y;
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selector uut (
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.select(select),
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.A(A),
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.B(B),
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.opCodeA(opCodeA),
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.ALUY(ALUY),
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.Y(Y)
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);
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initial begin
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$dumpfile("selector.vcd");
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$dumpvars;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b00; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b01; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b10; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b11; #5;
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$finish;
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end
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endmodule
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