63 lines
1.5 KiB
Verilog
63 lines
1.5 KiB
Verilog
module top (
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input clk, // Clock signal
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input [3:0] switches, // Slide switches SW3 to SW0
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input rot_a, rot_b, // Rotary encoder signals
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input rot_center, // Rotary encoder push button
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output lcd_rs, // LCD Register Select
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output lcd_rw, // LCD Read/Write
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output lcd_e, // LCD Enable
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output [7:4] lcd_d // LCD Data
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);
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// Internal signals
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wire [3:0] A;
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wire [3:0] B;
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wire [2:0] opCode;
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wire [7:0] Y;
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wire [4:0] mem_addr;
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wire [7:0] mem_bus;
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// ALU Instance
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ALU alu_inst (
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.A(A),
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.B(B),
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.CarryIN(1'b0), // No carry-in for this implementation
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.opCodeA(opCode),
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.Y(Y),
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.CarryOUT(), // Unused output
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.overflow() // Unused output
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);
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// Switch and Rotary Controller
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switch_and_rotary switch_rotary_inst (
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.clk(clk),
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.switches(switches),
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.rot_a(rot_a),
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.rot_b(rot_b),
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.rot_center(rot_center),
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.A(A),
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.B(B),
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.opCode(opCode)
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);
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// Character Memory
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char_mem char_mem_inst (
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.addr(mem_addr),
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.bus(mem_bus),
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.A(A),
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.B(B),
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.opCode(opCode),
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.Y(Y)
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);
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// LCD Controller
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lcd lcd_inst (
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.clk(clk),
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.lcd_rs(lcd_rs),
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.lcd_rw(lcd_rw),
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.lcd_e(lcd_e),
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.lcd_d(lcd_d),
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.mem_addr(mem_addr),
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.mem_bus(mem_bus)
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);
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endmodule
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