41 lines
917 B
Verilog
41 lines
917 B
Verilog
module BinaryToBCDTB;
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// Testbench signals
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reg [7:0] binary;
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wire [11:0] bcd; // Output BCD
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// Instantiate the BinaryToBCD module
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BinaryToBCD uut (
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.binary(binary),
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.bcd(bcd)
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);
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// Testbench procedure
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initial begin
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$monitor("Time: %0t | Binary: %b | BCD: %b (Hundreds: %d, Tens: %d, Ones: %d)",
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$time, binary, bcd, bcd[11:8], bcd[7:4], bcd[3:0]);
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$dumpfile("BinaryToBCD.vcd");
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$dumpvars;
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// Test cases
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binary = 8'b00000000; // Decimal: 0
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#10;
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binary = 8'b00001010; // Decimal: 10
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#10;
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binary = 8'b00101010; // Decimal: 42
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#10;
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binary = 8'b01100011; // Decimal: 99
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#10;
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binary = 8'b10011001; // Decimal: 153
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#10;
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binary = 8'b11111111; // Decimal: 255
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#10;
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// End simulation
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$finish;
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end
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endmodule
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