17 lines
672 B
Verilog
17 lines
672 B
Verilog
module subtraction (
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input [3:0] A, B,
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input BorrowIN,
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output [3:0] Y,
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output BorrowOUT //Overflow signal'ini yani negatif gonderecek
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);
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wire [3:0] tempB;
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// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
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fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
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fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
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fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
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fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOUT));
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endmodule
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