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verilog

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This commit is contained in:
k0rrluna
2024-05-07 16:15:21 +03:00
parent ed465dd690
commit 492a55d360
44 changed files with 11289 additions and 194 deletions
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52
lab3/impl/temp/rtl_parser.result
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@@ -1,10 +1,54 @@
[
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"InstLine" : 1,
"InstName" : "Adder3Bit",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
"InstName" : "fullAdder",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"ModuleLine" : 1,
"ModuleName" : "Adder3Bit"
"ModuleName" : "fullAdder",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
"InstLine" : 7,
"InstName" : "h0",
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
"ModuleLine" : 1,
"ModuleName" : "halfAdder"
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
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"InstName" : "h1",
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}
]
},
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
"InstLine" : 1,
"InstName" : "mult2bit",
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"ModuleLine" : 1,
"ModuleName" : "mult2bit",
"SubInsts" : [
{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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{
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
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}
]