verilog
This commit is contained in:
@@ -1,23 +1,27 @@
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v'
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ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
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ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
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ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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Sorry, too many errors..
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
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Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
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Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
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NOTE (EX0101) : Current top module is "mult2bit"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
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GowinSynthesis finish
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@@ -4,8 +4,9 @@
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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@@ -1,118 +1,137 @@
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//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Sat Apr 13 05:09:20 2024
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//Sat May 4 01:07:38 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v"
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//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
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//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
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//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
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`timescale 100 ps/100 ps
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module Adder3Bit (
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num1,
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num2,
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Carry,
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sum
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module halfAdder (
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A_d,
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B_d,
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C_d
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)
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;
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input [2:0] num1;
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input [2:0] num2;
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output [2:0] Carry;
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output [2:0] sum;
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wire [2:0] num1_d;
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wire [2:0] num2_d;
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wire [2:0] sum_d;
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wire [2:0] Carry_d;
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input [1:0] A_d;
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input [1:0] B_d;
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output [1:1] C_d;
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wire VCC;
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wire GND;
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IBUF num1_0_ibuf (
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.O(num1_d[0]),
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.I(num1[0])
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LUT4 C_d_1_s (
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.F(C_d[1]),
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.I0(A_d[1]),
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.I1(B_d[0]),
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.I2(A_d[0]),
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.I3(B_d[1])
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);
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IBUF num1_1_ibuf (
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.O(num1_d[1]),
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.I(num1[1])
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defparam C_d_1_s.INIT=16'h7888;
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VCC VCC_cZ (
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.V(VCC)
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);
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IBUF num1_2_ibuf (
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.O(num1_d[2]),
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.I(num1[2])
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GND GND_cZ (
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.G(GND)
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);
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IBUF num2_0_ibuf (
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.O(num2_d[0]),
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.I(num2[0])
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endmodule /* halfAdder */
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module halfAdder_0 (
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A_d,
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B_d,
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C_d
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)
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;
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input [1:0] A_d;
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input [1:0] B_d;
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output [3:2] C_d;
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wire VCC;
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wire GND;
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LUT4 C_d_3_s (
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.F(C_d[3]),
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.I0(A_d[0]),
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.I1(B_d[0]),
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.I2(A_d[1]),
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.I3(B_d[1])
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);
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IBUF num2_1_ibuf (
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.O(num2_d[1]),
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.I(num2[1])
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defparam C_d_3_s.INIT=16'h7000;
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LUT4 C_d_2_s (
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.F(C_d[2]),
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.I0(A_d[1]),
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.I1(B_d[0]),
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.I2(A_d[0]),
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.I3(B_d[1])
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);
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IBUF num2_2_ibuf (
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.O(num2_d[2]),
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.I(num2[2])
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defparam C_d_2_s.INIT=16'h8000;
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VCC VCC_cZ (
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.V(VCC)
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);
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OBUF Carry_0_obuf (
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.O(Carry[0]),
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.I(Carry_d[0])
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GND GND_cZ (
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.G(GND)
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);
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OBUF Carry_1_obuf (
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.O(Carry[1]),
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.I(Carry_d[1])
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endmodule /* halfAdder_0 */
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module mult2bit (
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A,
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B,
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C
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)
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;
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input [1:0] A;
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input [1:0] B;
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output [3:0] C;
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wire [1:0] A_d;
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wire [1:0] B_d;
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wire [0:0] C_d;
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wire [1:1] C_d_0;
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wire [3:2] C_d_1;
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wire VCC;
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wire GND;
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IBUF A_0_ibuf (
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.O(A_d[0]),
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.I(A[0])
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);
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OBUF Carry_2_obuf (
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.O(Carry[2]),
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.I(Carry_d[2])
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IBUF A_1_ibuf (
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.O(A_d[1]),
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.I(A[1])
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);
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OBUF sum_0_obuf (
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.O(sum[0]),
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.I(sum_d[0])
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IBUF B_0_ibuf (
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.O(B_d[0]),
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.I(B[0])
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);
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OBUF sum_1_obuf (
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.O(sum[1]),
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.I(sum_d[1])
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IBUF B_1_ibuf (
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.O(B_d[1]),
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.I(B[1])
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);
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OBUF sum_2_obuf (
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.O(sum[2]),
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.I(sum_d[2])
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OBUF C_0_obuf (
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.O(C[0]),
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.I(C_d[0])
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);
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LUT2 sum_d_0_s (
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.F(sum_d[0]),
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.I0(num1_d[0]),
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.I1(num2_d[0])
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OBUF C_1_obuf (
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.O(C[1]),
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.I(C_d_0[1])
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);
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defparam sum_d_0_s.INIT=4'h6;
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LUT2 Carry_d_0_s (
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.F(Carry_d[0]),
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.I0(num1_d[0]),
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.I1(num2_d[0])
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OBUF C_2_obuf (
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.O(C[2]),
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.I(C_d_1[2])
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);
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defparam Carry_d_0_s.INIT=4'h8;
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LUT4 Carry_d_1_s (
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.F(Carry_d[1]),
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.I0(num1_d[1]),
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.I1(num2_d[1]),
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.I2(num1_d[0]),
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.I3(num2_d[0])
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OBUF C_3_obuf (
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.O(C[3]),
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.I(C_d_1[3])
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);
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defparam Carry_d_1_s.INIT=16'hE888;
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LUT3 sum_d_2_s (
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.F(sum_d[2]),
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.I0(Carry_d[1]),
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.I1(num1_d[2]),
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.I2(num2_d[2])
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LUT2 C_d_0_s (
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.F(C_d[0]),
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.I0(B_d[0]),
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.I1(A_d[0])
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);
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defparam sum_d_2_s.INIT=8'h96;
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LUT3 Carry_d_2_s (
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.F(Carry_d[2]),
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.I0(Carry_d[1]),
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.I1(num1_d[2]),
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.I2(num2_d[2])
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defparam C_d_0_s.INIT=4'h8;
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halfAdder h0 (
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.A_d(A_d[1:0]),
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.B_d(B_d[1:0]),
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.C_d(C_d_0[1])
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);
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defparam Carry_d_2_s.INIT=8'hE8;
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LUT4 sum_d_1_s0 (
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.F(sum_d[1]),
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.I0(num1_d[0]),
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.I1(num2_d[0]),
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.I2(num1_d[1]),
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.I3(num2_d[1])
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halfAdder_0 h1 (
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.A_d(A_d[1:0]),
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.B_d(B_d[1:0]),
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.C_d(C_d_1[3:2])
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);
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defparam sum_d_1_s0.INIT=16'h8778;
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VCC VCC_cZ (
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.V(VCC)
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);
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@@ -122,4 +141,4 @@ defparam sum_d_1_s0.INIT=16'h8778;
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* Adder3Bit */
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endmodule /* mult2bit */
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@@ -48,7 +48,9 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
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</tr>
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<tr>
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<td class="label">Design File</td>
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<td>C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v<br>
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<td>C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v<br>
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C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v<br>
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C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v<br>
|
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</td>
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</tr>
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<tr>
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@@ -73,7 +75,7 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Sat Apr 13 05:09:20 2024
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<td>Sat May 4 01:07:38 2024
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</td>
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</tr>
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<tr>
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@@ -85,15 +87,15 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
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<table class="summary_table">
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<tr>
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<td class="label">Top Level Module</td>
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<td>Adder3Bit</td>
|
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<td>mult2bit</td>
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</tr>
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<tr>
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<td class="label">Synthesis Process</td>
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<td>Running parser:<br/> CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 156.254MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 156.254MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.254MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.254MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.254MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.301s, Peak memory usage = 172.207MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 172.207MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 172.207MB<br/></td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 417.762MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 417.762MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 172.207MB</td>
|
||||
<td>CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 417.762MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
@@ -105,35 +107,31 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>12</td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>12</td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>6</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>6</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>6</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT3</td>
|
||||
<td>2</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>2</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
@@ -145,7 +143,7 @@ table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>6(6 LUT, 0 ALU) / 20736</td>
|
||||
<td>4(4 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
|
||||
@@ -30,10 +30,30 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
|
||||
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">6</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h0
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h1
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">2</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
|
||||
@@ -1,2 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="Adder3Bit" Lut="6" T_Lut="6(6)"/>
|
||||
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
|
||||
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
|
||||
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
|
||||
</Module>
|
||||
|
||||
Reference in New Issue
Block a user