basic alu & simple fixes
This commit is contained in:
parent
cbf97501ea
commit
0f57860554
1479
project/ALU
Normal file
1479
project/ALU
Normal file
File diff suppressed because it is too large
Load Diff
57
project/ALU.v
Normal file
57
project/ALU.v
Normal file
@ -0,0 +1,57 @@
|
||||
module ALU (
|
||||
input [3:0] A, B,
|
||||
input CarryIN,
|
||||
input opCodeA, opCodeB, opCodeC,
|
||||
output [3:0] Y,
|
||||
output CarryOUT, overflow
|
||||
);
|
||||
|
||||
// Supports: ADD[0], SUB[1], AND[4], OR[5], XOR[6]
|
||||
|
||||
wire [7:0] opCode8;
|
||||
wire [3:0] add_Y, sub_Y;
|
||||
wire [3:0] resultA, resultO, resultX, lUOutput1;
|
||||
wire [3:0] aUtemp1, aUtemp2, lUOutput2;
|
||||
wire [3:0] wireY;
|
||||
|
||||
opCode opCd (.A(opCodeA), .B(opCodeB), .C(opCodeC), .opCode(opCode8));
|
||||
|
||||
arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
|
||||
logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
|
||||
|
||||
or o01 (lUOutput1[0], resultA[0], resultO[0]);
|
||||
or o02 (lUOutput1[1], resultA[1], resultO[1]);
|
||||
or o03 (lUOutput1[2], resultA[2], resultO[2]);
|
||||
or o04 (lUOutput1[3], resultA[3], resultO[3]);
|
||||
|
||||
or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
|
||||
or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
|
||||
or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
|
||||
or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
|
||||
|
||||
|
||||
and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
|
||||
and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
|
||||
and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
|
||||
and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
|
||||
|
||||
|
||||
and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
|
||||
and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
|
||||
and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
|
||||
and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
|
||||
|
||||
|
||||
or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
|
||||
or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
|
||||
or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
|
||||
or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
|
||||
|
||||
|
||||
or o1 (Y[0], lUOutput2[0], wireY[0]);
|
||||
or o2 (Y[1], lUOutput2[1], wireY[1]);
|
||||
or o3 (Y[2], lUOutput2[2], wireY[2]);
|
||||
or o4 (Y[3], lUOutput2[3], wireY[3]);
|
||||
|
||||
|
||||
endmodule
|
||||
1660
project/ALU.vcd
Normal file
1660
project/ALU.vcd
Normal file
File diff suppressed because it is too large
Load Diff
38
project/ALUTB.v
Normal file
38
project/ALUTB.v
Normal file
@ -0,0 +1,38 @@
|
||||
module ALUTB ();
|
||||
|
||||
reg [3:0] A, B;
|
||||
reg CarryIN;
|
||||
reg opCodeA, opCodeB, opCodeC;
|
||||
wire [3:0] Y;
|
||||
wire CarryOUT, overflow;
|
||||
|
||||
ALU uut(
|
||||
.A(A),
|
||||
.B(B),
|
||||
.CarryIN(CarryIN),
|
||||
.opCodeA(opCodeA),
|
||||
.opCodeB(opCodeB),
|
||||
.opCodeC(opCodeC),
|
||||
.Y(Y),
|
||||
.CarryOUT(CarryOUT),
|
||||
.overflow(overflow)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
|
||||
$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
|
||||
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
|
||||
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
|
||||
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
|
||||
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
|
||||
A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
|
||||
|
||||
A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
|
||||
A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
|
||||
A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
|
||||
A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
|
||||
A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
|
||||
$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,13 +1,20 @@
|
||||
module addition (
|
||||
input [3:0] A, B,
|
||||
output [4:0] Y
|
||||
input CarryIN,
|
||||
output [3:0] Y,
|
||||
output CarryOUT,
|
||||
output overflow
|
||||
);
|
||||
|
||||
wire [3:0] Carry4;
|
||||
|
||||
halfadder h1(.A(A[0]), .B(B[0]), .Sum(Y[0]), .Carry(Carry4[0]));
|
||||
fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
|
||||
fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
|
||||
fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
|
||||
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(Y[4]));
|
||||
fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
|
||||
|
||||
|
||||
overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow));
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
29
project/arithmeticUnit.v
Normal file
29
project/arithmeticUnit.v
Normal file
@ -0,0 +1,29 @@
|
||||
module arithmeticUnit (
|
||||
input [1:0] opCode,
|
||||
input [3:0] A, B,
|
||||
input CarryIN,
|
||||
output [3:0] add_Y, sub_Y,
|
||||
output CarryOUT,
|
||||
output overflow
|
||||
);
|
||||
|
||||
wire [3:0] addY, subY;
|
||||
wire overflowSUB, overflowADD, CarryOUTADD, CarryOUTSUB;
|
||||
|
||||
addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(overflowADD));
|
||||
subtraction s1(.A(A), .B(B), .CarryIN(CarryIN), .Y(subY), .CarryOUT(CarryOUTSUB), .overflow(overflowSUB));
|
||||
|
||||
and add1 (add_Y[0], opCode[0], addY[0]);
|
||||
and add2 (add_Y[1], opCode[0], addY[1]);
|
||||
and add3 (add_Y[2], opCode[0], addY[2]);
|
||||
and add4 (add_Y[3], opCode[0], addY[3]);
|
||||
|
||||
and sub1 (sub_Y[0], opCode[1], subY[0]);
|
||||
and sub2 (sub_Y[1], opCode[1], subY[1]);
|
||||
and sub3 (sub_Y[2], opCode[1], subY[2]);
|
||||
and sub4 (sub_Y[3], opCode[1], subY[3]);
|
||||
|
||||
or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB);
|
||||
or or2 (overflow, overflowADD, overflowSUB);
|
||||
|
||||
endmodule
|
||||
136
project/opCode
136
project/opCode
@ -7,114 +7,114 @@
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5595e35f5aa0 .scope module, "opCodeTB" "opCodeTB" 2 1;
|
||||
S_0x5607c3854aa0 .scope module, "opCodeTB" "opCodeTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5595e360d6f0_0 .var "A", 0 0;
|
||||
v0x5595e360d7b0_0 .var "B", 0 0;
|
||||
v0x5595e360d880_0 .var "C", 0 0;
|
||||
v0x5595e360d980_0 .net "opCode", 7 0, L_0x5595e360e5f0; 1 drivers
|
||||
S_0x5595e35f5c30 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5595e35f5aa0;
|
||||
v0x5607c386c6f0_0 .var "A", 0 0;
|
||||
v0x5607c386c7b0_0 .var "B", 0 0;
|
||||
v0x5607c386c880_0 .var "C", 0 0;
|
||||
v0x5607c386c980_0 .net "opCode", 7 0, L_0x5607c386d5f0; 1 drivers
|
||||
S_0x5607c3854c30 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5607c3854aa0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /OUTPUT 8 "opCode";
|
||||
L_0x5595e360da50 .functor NOT 1, v0x5595e360d6f0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5595e360daf0 .functor NOT 1, v0x5595e360d7b0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5595e360dbb0 .functor NOT 1, v0x5595e360d880_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5595e360dc70 .functor AND 1, v0x5595e360d6f0_0, v0x5595e360d7b0_0, C4<1>, C4<1>;
|
||||
L_0x5595e360dd10 .functor AND 1, L_0x5595e360da50, v0x5595e360d7b0_0, C4<1>, C4<1>;
|
||||
L_0x5595e360de00 .functor AND 1, v0x5595e360d6f0_0, L_0x5595e360daf0, C4<1>, C4<1>;
|
||||
L_0x5595e360deb0 .functor AND 1, L_0x5595e360da50, L_0x5595e360daf0, C4<1>, C4<1>;
|
||||
L_0x5595e360df20 .functor AND 1, L_0x5595e360deb0, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e030 .functor AND 1, L_0x5595e360deb0, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
L_0x5595e360e0a0 .functor AND 1, L_0x5595e360dd10, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e1c0 .functor AND 1, L_0x5595e360dd10, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
L_0x5595e360e2c0 .functor AND 1, L_0x5595e360de00, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e460 .functor AND 1, L_0x5595e360de00, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
L_0x5595e360e4d0 .functor AND 1, L_0x5595e360dc70, L_0x5595e360dbb0, C4<1>, C4<1>;
|
||||
L_0x5595e360e3f0 .functor AND 1, L_0x5595e360dc70, v0x5595e360d880_0, C4<1>, C4<1>;
|
||||
v0x5595e35e0f30_0 .net "A", 0 0, v0x5595e360d6f0_0; 1 drivers
|
||||
v0x5595e35e0ae0_0 .net "B", 0 0, v0x5595e360d7b0_0; 1 drivers
|
||||
v0x5595e35e0690_0 .net "C", 0 0, v0x5595e360d880_0; 1 drivers
|
||||
v0x5595e35e0240_0 .net *"_ivl_0", 0 0, L_0x5595e360df20; 1 drivers
|
||||
v0x5595e35dfdf0_0 .net *"_ivl_10", 0 0, L_0x5595e360e460; 1 drivers
|
||||
v0x5595e35df970_0 .net *"_ivl_12", 0 0, L_0x5595e360e4d0; 1 drivers
|
||||
v0x5595e360cbf0_0 .net *"_ivl_14", 0 0, L_0x5595e360e3f0; 1 drivers
|
||||
v0x5595e360ccd0_0 .net *"_ivl_2", 0 0, L_0x5595e360e030; 1 drivers
|
||||
v0x5595e360cdb0_0 .net *"_ivl_4", 0 0, L_0x5595e360e0a0; 1 drivers
|
||||
v0x5595e360ce90_0 .net *"_ivl_6", 0 0, L_0x5595e360e1c0; 1 drivers
|
||||
v0x5595e360cf70_0 .net *"_ivl_8", 0 0, L_0x5595e360e2c0; 1 drivers
|
||||
v0x5595e360d050_0 .net "and1", 0 0, L_0x5595e360dc70; 1 drivers
|
||||
v0x5595e360d110_0 .net "and2", 0 0, L_0x5595e360dd10; 1 drivers
|
||||
v0x5595e360d1d0_0 .net "and3", 0 0, L_0x5595e360de00; 1 drivers
|
||||
v0x5595e360d290_0 .net "and4", 0 0, L_0x5595e360deb0; 1 drivers
|
||||
v0x5595e360d350_0 .net "notA", 0 0, L_0x5595e360da50; 1 drivers
|
||||
v0x5595e360d410_0 .net "notB", 0 0, L_0x5595e360daf0; 1 drivers
|
||||
v0x5595e360d4d0_0 .net "notC", 0 0, L_0x5595e360dbb0; 1 drivers
|
||||
v0x5595e360d590_0 .net "opCode", 7 0, L_0x5595e360e5f0; alias, 1 drivers
|
||||
LS_0x5595e360e5f0_0_0 .concat8 [ 1 1 1 1], L_0x5595e360df20, L_0x5595e360e030, L_0x5595e360e0a0, L_0x5595e360e1c0;
|
||||
LS_0x5595e360e5f0_0_4 .concat8 [ 1 1 1 1], L_0x5595e360e2c0, L_0x5595e360e460, L_0x5595e360e4d0, L_0x5595e360e3f0;
|
||||
L_0x5595e360e5f0 .concat8 [ 4 4 0 0], LS_0x5595e360e5f0_0_0, LS_0x5595e360e5f0_0_4;
|
||||
.scope S_0x5595e35f5aa0;
|
||||
L_0x5607c386ca50 .functor NOT 1, v0x5607c386c6f0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5607c386caf0 .functor NOT 1, v0x5607c386c7b0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5607c386cbb0 .functor NOT 1, v0x5607c386c880_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5607c386cc70 .functor AND 1, v0x5607c386c6f0_0, v0x5607c386c7b0_0, C4<1>, C4<1>;
|
||||
L_0x5607c386cd10 .functor AND 1, L_0x5607c386ca50, v0x5607c386c7b0_0, C4<1>, C4<1>;
|
||||
L_0x5607c386ce00 .functor AND 1, v0x5607c386c6f0_0, L_0x5607c386caf0, C4<1>, C4<1>;
|
||||
L_0x5607c386ceb0 .functor AND 1, L_0x5607c386ca50, L_0x5607c386caf0, C4<1>, C4<1>;
|
||||
L_0x5607c386cf20 .functor AND 1, L_0x5607c386ceb0, L_0x5607c386cbb0, C4<1>, C4<1>;
|
||||
L_0x5607c386d030 .functor AND 1, L_0x5607c386ceb0, v0x5607c386c880_0, C4<1>, C4<1>;
|
||||
L_0x5607c386d0a0 .functor AND 1, L_0x5607c386cd10, L_0x5607c386cbb0, C4<1>, C4<1>;
|
||||
L_0x5607c386d1c0 .functor AND 1, L_0x5607c386cd10, v0x5607c386c880_0, C4<1>, C4<1>;
|
||||
L_0x5607c386d2c0 .functor AND 1, L_0x5607c386ce00, L_0x5607c386cbb0, C4<1>, C4<1>;
|
||||
L_0x5607c386d460 .functor AND 1, L_0x5607c386ce00, v0x5607c386c880_0, C4<1>, C4<1>;
|
||||
L_0x5607c386d4d0 .functor AND 1, L_0x5607c386cc70, L_0x5607c386cbb0, C4<1>, C4<1>;
|
||||
L_0x5607c386d3f0 .functor AND 1, L_0x5607c386cc70, v0x5607c386c880_0, C4<1>, C4<1>;
|
||||
v0x5607c383ff30_0 .net "A", 0 0, v0x5607c386c6f0_0; 1 drivers
|
||||
v0x5607c383fae0_0 .net "B", 0 0, v0x5607c386c7b0_0; 1 drivers
|
||||
v0x5607c383f690_0 .net "C", 0 0, v0x5607c386c880_0; 1 drivers
|
||||
v0x5607c383f240_0 .net *"_ivl_0", 0 0, L_0x5607c386cf20; 1 drivers
|
||||
v0x5607c383edf0_0 .net *"_ivl_10", 0 0, L_0x5607c386d460; 1 drivers
|
||||
v0x5607c383e970_0 .net *"_ivl_12", 0 0, L_0x5607c386d4d0; 1 drivers
|
||||
v0x5607c386bbf0_0 .net *"_ivl_14", 0 0, L_0x5607c386d3f0; 1 drivers
|
||||
v0x5607c386bcd0_0 .net *"_ivl_2", 0 0, L_0x5607c386d030; 1 drivers
|
||||
v0x5607c386bdb0_0 .net *"_ivl_4", 0 0, L_0x5607c386d0a0; 1 drivers
|
||||
v0x5607c386be90_0 .net *"_ivl_6", 0 0, L_0x5607c386d1c0; 1 drivers
|
||||
v0x5607c386bf70_0 .net *"_ivl_8", 0 0, L_0x5607c386d2c0; 1 drivers
|
||||
v0x5607c386c050_0 .net "and1", 0 0, L_0x5607c386cc70; 1 drivers
|
||||
v0x5607c386c110_0 .net "and2", 0 0, L_0x5607c386cd10; 1 drivers
|
||||
v0x5607c386c1d0_0 .net "and3", 0 0, L_0x5607c386ce00; 1 drivers
|
||||
v0x5607c386c290_0 .net "and4", 0 0, L_0x5607c386ceb0; 1 drivers
|
||||
v0x5607c386c350_0 .net "notA", 0 0, L_0x5607c386ca50; 1 drivers
|
||||
v0x5607c386c410_0 .net "notB", 0 0, L_0x5607c386caf0; 1 drivers
|
||||
v0x5607c386c4d0_0 .net "notC", 0 0, L_0x5607c386cbb0; 1 drivers
|
||||
v0x5607c386c590_0 .net "opCode", 7 0, L_0x5607c386d5f0; alias, 1 drivers
|
||||
LS_0x5607c386d5f0_0_0 .concat8 [ 1 1 1 1], L_0x5607c386cf20, L_0x5607c386d030, L_0x5607c386d0a0, L_0x5607c386d1c0;
|
||||
LS_0x5607c386d5f0_0_4 .concat8 [ 1 1 1 1], L_0x5607c386d2c0, L_0x5607c386d460, L_0x5607c386d4d0, L_0x5607c386d3f0;
|
||||
L_0x5607c386d5f0 .concat8 [ 4 4 0 0], LS_0x5607c386d5f0_0_0, LS_0x5607c386d5f0_0_4;
|
||||
.scope S_0x5607c3854aa0;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "opCode.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d6f0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d7b0_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5595e360d880_0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%delay 3, 0;
|
||||
%vpi_call 2 24 "$finish" {0 0 0};
|
||||
%end;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Dec 13 20:24:01 2024
|
||||
Sun Dec 15 00:28:47 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@ -1,25 +1,29 @@
|
||||
module overflowDetect (
|
||||
input [1:0] opCode,
|
||||
input [3:0] A, B,
|
||||
input [4:0] Y,
|
||||
input [3:0] Y,
|
||||
input CarryOUT,
|
||||
output overflowDetect
|
||||
);
|
||||
|
||||
wire opC,AandSum;
|
||||
wire opC;
|
||||
wire sign1, sign2, sign3, sign4;
|
||||
wire addOverflow, subOverflow;
|
||||
wire detect1, detect2;
|
||||
|
||||
or o1 (opC, opCode[0], opCode[1]);
|
||||
xor xo1 (AandSum, Y[4], A[3]);
|
||||
or o1 (opC, opCode[0], opCode[1]); //check add or sub
|
||||
|
||||
and a1 (sign1, A[3], B[3]);
|
||||
or o2 (sign2, opCode[0], sign1);
|
||||
xnor xno1 (sign1, A[3], B[3]); // A B same sign
|
||||
xor xo2 (sign3, A[3], B[3]); // A and B opposite sign
|
||||
|
||||
xor a2 (sign3, A[3], B[3]);
|
||||
or o3 (sign4, opCode[1], sign3);
|
||||
xor xo1 (sign2, Y[3], A[3]); // A and Sum opposite sign
|
||||
|
||||
or o4 (detect1, sign2, sign4);
|
||||
and a3 (detect2, AandSum, opC);
|
||||
and a4 (overflowDetect, detect1, detect2);
|
||||
and a01 (addOverflow, sign1, opCode[0]); // A B same for add
|
||||
and a02 (subOverflow, sign3, opCode[1]); // A B diff for sub
|
||||
|
||||
or o2 (detect1, addOverflow, subOverflow);
|
||||
|
||||
and a03(detect2, detect1, sign2);
|
||||
and a04(overflowDetect, opC, detect2);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,27 +1,27 @@
|
||||
module subtraction (
|
||||
input [3:0] A, B,
|
||||
output [4:0] Y
|
||||
input CarryIN,
|
||||
output [3:0] Y,
|
||||
output CarryOUT,
|
||||
output overflow
|
||||
);
|
||||
|
||||
wire [3:0] xB;
|
||||
wire [4:0] notB;
|
||||
wire [4:0] Y1;
|
||||
wire overflow;
|
||||
wire [3:0] notB;
|
||||
wire [3:0] Y1;
|
||||
|
||||
not n1 (xB[0], B[0]);
|
||||
not n2 (xB[1], B[1]);
|
||||
not n3 (xB[2], B[2]);
|
||||
not n4 (xB[3], B[3]);
|
||||
|
||||
addition a1 (.A(xB), .B(4'b0001), .Y(notB));
|
||||
addition a2 (.A(A), .B(notB[3:0]), .Y(Y1));
|
||||
overflowDetect od1 (.opCode(2'b10), .A(A), .B(B), .Y(Y1), .overflowDetect(overflow));
|
||||
addition a1 (.A(xB), .B(4'b0001), .CarryIN(1'b0), .Y(notB));
|
||||
addition a2 (.A(A), .B(notB[3:0]), .CarryIN(CarryIN), .Y(Y1), .CarryOUT(CarryOUT));
|
||||
overflowDetect od1 (.opCode(2'b10), .A(A), .B(B), .Y(Y1), .CarryOUT(CarryOUT), .overflowDetect(overflow));
|
||||
|
||||
or o1 (Y[0], Y1[0], 1'b0);
|
||||
or o2 (Y[1], Y1[1], 1'b0);
|
||||
or o3 (Y[2], Y1[2], 1'b0);
|
||||
or o4 (Y[3], Y1[3], 1'b0);
|
||||
|
||||
xor(Y[4], overflow, Y1[4]);
|
||||
|
||||
endmodule
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user