verilog/project/ALU.vcd

$date
	Sun Dec 15 03:49:14 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module ALUTB $end
$var wire 1 ! overflow $end
$var wire 4 " Y [3:0] $end
$var wire 1 # CarryOUT $end
$var reg 4 $ A [3:0] $end
$var reg 4 % B [3:0] $end
$var reg 1 & CarryIN $end
$var reg 1 ' opCodeA $end
$var reg 1 ( opCodeB $end
$var reg 1 ) opCodeC $end
$scope module uut $end
$var wire 4 * A [3:0] $end
$var wire 4 + B [3:0] $end
$var wire 1 & CarryIN $end
$var wire 1 ' opCodeA $end
$var wire 1 ( opCodeB $end
$var wire 1 ) opCodeC $end
$var wire 4 , wireY [3:0] $end
$var wire 4 - sub_Y [3:0] $end
$var wire 4 . resultX [3:0] $end
$var wire 4 / resultO [3:0] $end
$var wire 4 0 resultA [3:0] $end
$var wire 1 ! overflow $end
$var wire 8 1 opCode8 [7:0] $end
$var wire 4 2 lUOutput2 [3:0] $end
$var wire 4 3 lUOutput1 [3:0] $end
$var wire 4 4 add_Y [3:0] $end
$var wire 4 5 aUtemp2 [3:0] $end
$var wire 4 6 aUtemp1 [3:0] $end
$var wire 4 7 Y [3:0] $end
$var wire 1 # CarryOUT $end
$scope module aU $end
$var wire 4 8 A [3:0] $end
$var wire 4 9 B [3:0] $end
$var wire 1 & CarryIN $end
$var wire 1 # CarryOUT $end
$var wire 2 : opCode [1:0] $end
$var wire 1 ! overflow $end
$var wire 4 ; sub_Y [3:0] $end
$var wire 4 < subY [3:0] $end
$var wire 1 = overflowSUB $end
$var wire 1 > overflowADD $end
$var wire 4 ? add_Y [3:0] $end
$var wire 4 @ addY [3:0] $end
$var wire 1 A CarryOUTSUB $end
$var wire 1 B CarryOUTADD $end
$scope module a1 $end
$var wire 4 C A [3:0] $end
$var wire 4 D B [3:0] $end
$var wire 1 & CarryIN $end
$var wire 1 > overflow $end
$var wire 4 E Y [3:0] $end
$var wire 1 B CarryOUT $end
$var wire 4 F Carry4 [3:0] $end
$scope module f0 $end
$var wire 1 G A $end
$var wire 1 H B $end
$var wire 1 & Carry $end
$var wire 1 I CarryO $end
$var wire 1 J xor1 $end
$var wire 1 K and2 $end
$var wire 1 L and1 $end
$var wire 1 M Sum $end
$scope module h1 $end
$var wire 1 G A $end
$var wire 1 H B $end
$var wire 1 L Carry $end
$var wire 1 J Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 J A $end
$var wire 1 & B $end
$var wire 1 K Carry $end
$var wire 1 M Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 N A $end
$var wire 1 O B $end
$var wire 1 P Carry $end
$var wire 1 Q CarryO $end
$var wire 1 R xor1 $end
$var wire 1 S and2 $end
$var wire 1 T and1 $end
$var wire 1 U Sum $end
$scope module h1 $end
$var wire 1 N A $end
$var wire 1 O B $end
$var wire 1 T Carry $end
$var wire 1 R Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 R A $end
$var wire 1 P B $end
$var wire 1 S Carry $end
$var wire 1 U Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 V A $end
$var wire 1 W B $end
$var wire 1 X Carry $end
$var wire 1 Y CarryO $end
$var wire 1 Z xor1 $end
$var wire 1 [ and2 $end
$var wire 1 \ and1 $end
$var wire 1 ] Sum $end
$scope module h1 $end
$var wire 1 V A $end
$var wire 1 W B $end
$var wire 1 \ Carry $end
$var wire 1 Z Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 Z A $end
$var wire 1 X B $end
$var wire 1 [ Carry $end
$var wire 1 ] Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 ^ A $end
$var wire 1 _ B $end
$var wire 1 ` Carry $end
$var wire 1 B CarryO $end
$var wire 1 a xor1 $end
$var wire 1 b and2 $end
$var wire 1 c and1 $end
$var wire 1 d Sum $end
$scope module h1 $end
$var wire 1 ^ A $end
$var wire 1 _ B $end
$var wire 1 c Carry $end
$var wire 1 a Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 a A $end
$var wire 1 ` B $end
$var wire 1 b Carry $end
$var wire 1 d Sum $end
$upscope $end
$upscope $end
$scope module od1 $end
$var wire 4 e A [3:0] $end
$var wire 4 f B [3:0] $end
$var wire 1 B CarryOUT $end
$var wire 4 g Y [3:0] $end
$var wire 1 h addOverflow $end
$var wire 1 i detect1 $end
$var wire 1 j detect2 $end
$var wire 1 k opC $end
$var wire 2 l opCode [1:0] $end
$var wire 1 > overflowDetect $end
$var wire 1 m sign1 $end
$var wire 1 n sign2 $end
$var wire 1 o sign3 $end
$var wire 1 p subOverflow $end
$upscope $end
$upscope $end
$scope module s1 $end
$var wire 4 q A [3:0] $end
$var wire 4 r B [3:0] $end
$var wire 1 & CarryIN $end
$var wire 4 s xB [3:0] $end
$var wire 1 = overflow $end
$var wire 4 t notB [3:0] $end
$var wire 4 u Y1 [3:0] $end
$var wire 4 v Y [3:0] $end
$var wire 1 A CarryOUT $end
$scope module a1 $end
$var wire 4 w A [3:0] $end
$var wire 4 x B [3:0] $end
$var wire 1 y CarryIN $end
$var wire 1 z overflow $end
$var wire 4 { Y [3:0] $end
$var wire 1 | CarryOUT $end
$var wire 4 } Carry4 [3:0] $end
$scope module f0 $end
$var wire 1 ~ A $end
$var wire 1 !" B $end
$var wire 1 y Carry $end
$var wire 1 "" CarryO $end
$var wire 1 #" xor1 $end
$var wire 1 $" and2 $end
$var wire 1 %" and1 $end
$var wire 1 &" Sum $end
$scope module h1 $end
$var wire 1 ~ A $end
$var wire 1 !" B $end
$var wire 1 %" Carry $end
$var wire 1 #" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 #" A $end
$var wire 1 y B $end
$var wire 1 $" Carry $end
$var wire 1 &" Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 '" A $end
$var wire 1 (" B $end
$var wire 1 )" Carry $end
$var wire 1 *" CarryO $end
$var wire 1 +" xor1 $end
$var wire 1 ," and2 $end
$var wire 1 -" and1 $end
$var wire 1 ." Sum $end
$scope module h1 $end
$var wire 1 '" A $end
$var wire 1 (" B $end
$var wire 1 -" Carry $end
$var wire 1 +" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 +" A $end
$var wire 1 )" B $end
$var wire 1 ," Carry $end
$var wire 1 ." Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 /" A $end
$var wire 1 0" B $end
$var wire 1 1" Carry $end
$var wire 1 2" CarryO $end
$var wire 1 3" xor1 $end
$var wire 1 4" and2 $end
$var wire 1 5" and1 $end
$var wire 1 6" Sum $end
$scope module h1 $end
$var wire 1 /" A $end
$var wire 1 0" B $end
$var wire 1 5" Carry $end
$var wire 1 3" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 3" A $end
$var wire 1 1" B $end
$var wire 1 4" Carry $end
$var wire 1 6" Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 7" A $end
$var wire 1 8" B $end
$var wire 1 9" Carry $end
$var wire 1 | CarryO $end
$var wire 1 :" xor1 $end
$var wire 1 ;" and2 $end
$var wire 1 <" and1 $end
$var wire 1 =" Sum $end
$scope module h1 $end
$var wire 1 7" A $end
$var wire 1 8" B $end
$var wire 1 <" Carry $end
$var wire 1 :" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 :" A $end
$var wire 1 9" B $end
$var wire 1 ;" Carry $end
$var wire 1 =" Sum $end
$upscope $end
$upscope $end
$scope module od1 $end
$var wire 4 >" A [3:0] $end
$var wire 4 ?" B [3:0] $end
$var wire 1 | CarryOUT $end
$var wire 4 @" Y [3:0] $end
$var wire 1 A" addOverflow $end
$var wire 1 B" detect1 $end
$var wire 1 C" detect2 $end
$var wire 1 D" opC $end
$var wire 2 E" opCode [1:0] $end
$var wire 1 z overflowDetect $end
$var wire 1 F" sign1 $end
$var wire 1 G" sign2 $end
$var wire 1 H" sign3 $end
$var wire 1 I" subOverflow $end
$upscope $end
$upscope $end
$scope module a2 $end
$var wire 4 J" A [3:0] $end
$var wire 4 K" B [3:0] $end
$var wire 1 & CarryIN $end
$var wire 1 L" overflow $end
$var wire 4 M" Y [3:0] $end
$var wire 1 A CarryOUT $end
$var wire 4 N" Carry4 [3:0] $end
$scope module f0 $end
$var wire 1 O" A $end
$var wire 1 P" B $end
$var wire 1 & Carry $end
$var wire 1 Q" CarryO $end
$var wire 1 R" xor1 $end
$var wire 1 S" and2 $end
$var wire 1 T" and1 $end
$var wire 1 U" Sum $end
$scope module h1 $end
$var wire 1 O" A $end
$var wire 1 P" B $end
$var wire 1 T" Carry $end
$var wire 1 R" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 R" A $end
$var wire 1 & B $end
$var wire 1 S" Carry $end
$var wire 1 U" Sum $end
$upscope $end
$upscope $end
$scope module f1 $end
$var wire 1 V" A $end
$var wire 1 W" B $end
$var wire 1 X" Carry $end
$var wire 1 Y" CarryO $end
$var wire 1 Z" xor1 $end
$var wire 1 [" and2 $end
$var wire 1 \" and1 $end
$var wire 1 ]" Sum $end
$scope module h1 $end
$var wire 1 V" A $end
$var wire 1 W" B $end
$var wire 1 \" Carry $end
$var wire 1 Z" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 Z" A $end
$var wire 1 X" B $end
$var wire 1 [" Carry $end
$var wire 1 ]" Sum $end
$upscope $end
$upscope $end
$scope module f2 $end
$var wire 1 ^" A $end
$var wire 1 _" B $end
$var wire 1 `" Carry $end
$var wire 1 a" CarryO $end
$var wire 1 b" xor1 $end
$var wire 1 c" and2 $end
$var wire 1 d" and1 $end
$var wire 1 e" Sum $end
$scope module h1 $end
$var wire 1 ^" A $end
$var wire 1 _" B $end
$var wire 1 d" Carry $end
$var wire 1 b" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 b" A $end
$var wire 1 `" B $end
$var wire 1 c" Carry $end
$var wire 1 e" Sum $end
$upscope $end
$upscope $end
$scope module f3 $end
$var wire 1 f" A $end
$var wire 1 g" B $end
$var wire 1 h" Carry $end
$var wire 1 A CarryO $end
$var wire 1 i" xor1 $end
$var wire 1 j" and2 $end
$var wire 1 k" and1 $end
$var wire 1 l" Sum $end
$scope module h1 $end
$var wire 1 f" A $end
$var wire 1 g" B $end
$var wire 1 k" Carry $end
$var wire 1 i" Sum $end
$upscope $end
$scope module h2 $end
$var wire 1 i" A $end
$var wire 1 h" B $end
$var wire 1 j" Carry $end
$var wire 1 l" Sum $end
$upscope $end
$upscope $end
$scope module od1 $end
$var wire 4 m" A [3:0] $end
$var wire 4 n" B [3:0] $end
$var wire 1 A CarryOUT $end
$var wire 4 o" Y [3:0] $end
$var wire 1 p" addOverflow $end
$var wire 1 q" detect1 $end
$var wire 1 r" detect2 $end
$var wire 1 s" opC $end
$var wire 2 t" opCode [1:0] $end
$var wire 1 L" overflowDetect $end
$var wire 1 u" sign1 $end
$var wire 1 v" sign2 $end
$var wire 1 w" sign3 $end
$var wire 1 x" subOverflow $end
$upscope $end
$upscope $end
$scope module od1 $end
$var wire 4 y" A [3:0] $end
$var wire 4 z" B [3:0] $end
$var wire 1 A CarryOUT $end
$var wire 4 {" Y [3:0] $end
$var wire 1 |" addOverflow $end
$var wire 1 }" detect1 $end
$var wire 1 ~" detect2 $end
$var wire 1 !# opC $end
$var wire 2 "# opCode [1:0] $end
$var wire 1 = overflowDetect $end
$var wire 1 ## sign1 $end
$var wire 1 $# sign2 $end
$var wire 1 %# sign3 $end
$var wire 1 &# subOverflow $end
$upscope $end
$upscope $end
$upscope $end
$scope module lU $end
$var wire 4 '# A [3:0] $end
$var wire 4 (# B [3:0] $end
$var wire 3 )# opCode [2:0] $end
$var wire 4 *# xor1 [3:0] $end
$var wire 4 +# resultX [3:0] $end
$var wire 4 ,# resultO [3:0] $end
$var wire 4 -# resultA [3:0] $end
$var wire 4 .# or1 [3:0] $end
$var wire 4 /# and1 [3:0] $end
$upscope $end
$scope module opCd $end
$var wire 1 ' A $end
$var wire 1 ( B $end
$var wire 1 ) C $end
$var wire 1 0# and1 $end
$var wire 1 1# and2 $end
$var wire 1 2# and3 $end
$var wire 1 3# and4 $end
$var wire 1 4# notA $end
$var wire 1 5# notB $end
$var wire 1 6# notC $end
$var wire 8 7# opCode [7:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
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