81 lines
990 B
Plaintext
81 lines
990 B
Plaintext
$date
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Wed Jan 8 01:16:47 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module selectorTB $end
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$var wire 8 ! s0 [7:0] $end
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$var reg 4 " A [3:0] $end
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$var reg 4 # B [3:0] $end
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$var reg 8 $ Y [7:0] $end
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$var reg 3 % opCodeA [2:0] $end
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$var reg 4 & select [3:0] $end
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$scope module uut $end
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$var wire 4 ' A [3:0] $end
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$var wire 4 ( B [3:0] $end
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$var wire 8 ) Y [7:0] $end
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$var wire 3 * opCodeA [2:0] $end
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$var wire 4 + select [3:0] $end
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$var wire 8 , y0 [7:0] $end
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$var wire 4 - tempYO [3:0] $end
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$var wire 4 . tempAB [3:0] $end
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$var wire 8 / s0 [7:0] $end
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$var wire 3 0 op0 [2:0] $end
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$var wire 4 1 b0 [3:0] $end
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$var wire 4 2 a0 [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b0 2
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b10 1
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b0 0
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b10 /
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b10 .
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b0 -
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b0 ,
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b10 +
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b111 *
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bz )
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b10 (
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b1 '
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b10 &
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b111 %
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b11110000 $
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b10 #
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b1 "
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b10 !
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$end
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#5
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b1 !
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b1 /
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b1 .
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b1 2
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b0 1
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b1 &
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b1 +
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#10
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b0 .
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bx -
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bx !
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bx /
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b0 2
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bx ,
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b100 &
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b100 +
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b1110000 $
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#15
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b111 -
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b111 !
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b111 /
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b0 ,
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b111 0
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b1000 &
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b1000 +
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#20
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