17 lines
189 B
Verilog
17 lines
189 B
Verilog
module mux2 (
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input A0, A1,
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input S,
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output Y
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);
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wire notS, and1, and2;
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not n1 (notS, S);
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and an1 (and1, A1, S);
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and an2 (and2, notS, A0);
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or o1 (Y, and1, and2);
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endmodule
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