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kaltinsoy
/
verilog
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verilog
/
gowin
/
fpga_project
/
impl
/
gwsynthesis
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k0rrluna
0237c7bcb2
rearrangement
2024-12-01 02:01:08 +03:00
..
fpga_project_syn_resource.html
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fpga_project_syn_rsc.xml
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2024-12-01 02:01:08 +03:00
fpga_project_syn.rpt.html
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2024-12-01 02:01:08 +03:00
fpga_project.log
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2024-12-01 02:01:08 +03:00
fpga_project.prj
rearrangement
2024-12-01 02:01:08 +03:00
fpga_project.vg
rearrangement
2024-12-01 02:01:08 +03:00
