kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
verilog/gowin/fpga_project
History
k0rrluna 0237c7bcb2 rearrangement
2024-12-01 02:01:08 +03:00
..
impl
rearrangement
2024-12-01 02:01:08 +03:00
src
rearrangement
2024-12-01 02:01:08 +03:00
fpga_project.gprj
rearrangement
2024-12-01 02:01:08 +03:00
fpga_project.gprj.user
rearrangement
2024-12-01 02:01:08 +03:00