verilog/gowin/fpga_project/impl/gwsynthesis/fpga_project_syn_rsc.xml
2024-12-01 02:01:08 +03:00

3 lines
87 B
XML

<?xml version="1.0" encoding="UTF-8"?>
<Module name="ledTest" Lut="2" T_Lut="2(2)"/>