verilog

lab3/impl/temp/rtl_parser.result

@@ -0,0 +1,10 @@
+[
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+  "InstLine" : 1,
+  "InstName" : "Adder3Bit",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "Adder3Bit"
+ }
+]

lab3/impl/temp/rtl_parser_arg.json

@@ -0,0 +1,21 @@
+{
+ "Device" : "GW2A-18C",
+ "Files" : [
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v",
+   "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/cygwin64/home/koray/verilog/lab3/src/tbAdder3Bit.v",
+   "Type" : "verilog"
+  }
+ ],
+ "IncludePath" : [
+
+ ],
+ "LoopLimit" : 2000,
+ "ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result",
+ "Top" : "",
+ "VerilogStd" : "verilog_2001",
+ "VhdlStd" : "vhdl_93"
+}