verilog
This commit is contained in:
23
lab3/impl/gwsynthesis/lab3.log
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23
lab3/impl/gwsynthesis/lab3.log
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@ -0,0 +1,23 @@
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v'
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ERROR (EX3615) : '.name implicit port connection' is not allowed in this dialect, use SystemVerilog mode instead("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
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ERROR (EX3863) : Syntax error near '['("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":7)
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ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":16)
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ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":17)
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ERROR (EX3994) : Cannot assign to memory 'r1' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3356) : Unpacked value/target cannot be used in an assignment("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3994) : Cannot assign to memory 'r2' directly("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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ERROR (EX3651) : Cannot assign a packed type to an unpacked type("C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v":18)
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Sorry, too many errors..
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GowinSynthesis finish
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20
lab3/impl/gwsynthesis/lab3.prj
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20
lab3/impl/gwsynthesis/lab3.prj
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@ -0,0 +1,20 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\tbAdder3Bit.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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125
lab3/impl/gwsynthesis/lab3.vg
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125
lab3/impl/gwsynthesis/lab3.vg
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@ -0,0 +1,125 @@
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//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Sat Apr 13 05:09:20 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v"
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`timescale 100 ps/100 ps
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module Adder3Bit (
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num1,
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num2,
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Carry,
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sum
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)
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;
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input [2:0] num1;
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input [2:0] num2;
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output [2:0] Carry;
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output [2:0] sum;
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wire [2:0] num1_d;
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wire [2:0] num2_d;
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wire [2:0] sum_d;
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wire [2:0] Carry_d;
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wire VCC;
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wire GND;
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IBUF num1_0_ibuf (
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.O(num1_d[0]),
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.I(num1[0])
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);
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IBUF num1_1_ibuf (
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.O(num1_d[1]),
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.I(num1[1])
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);
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IBUF num1_2_ibuf (
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.O(num1_d[2]),
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.I(num1[2])
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);
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IBUF num2_0_ibuf (
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.O(num2_d[0]),
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.I(num2[0])
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);
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IBUF num2_1_ibuf (
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.O(num2_d[1]),
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.I(num2[1])
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);
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IBUF num2_2_ibuf (
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.O(num2_d[2]),
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.I(num2[2])
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);
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OBUF Carry_0_obuf (
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.O(Carry[0]),
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.I(Carry_d[0])
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);
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OBUF Carry_1_obuf (
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.O(Carry[1]),
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.I(Carry_d[1])
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);
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OBUF Carry_2_obuf (
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.O(Carry[2]),
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.I(Carry_d[2])
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);
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OBUF sum_0_obuf (
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.O(sum[0]),
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.I(sum_d[0])
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);
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OBUF sum_1_obuf (
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.O(sum[1]),
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.I(sum_d[1])
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);
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OBUF sum_2_obuf (
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.O(sum[2]),
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.I(sum_d[2])
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);
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LUT2 sum_d_0_s (
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.F(sum_d[0]),
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.I0(num1_d[0]),
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.I1(num2_d[0])
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);
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defparam sum_d_0_s.INIT=4'h6;
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LUT2 Carry_d_0_s (
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.F(Carry_d[0]),
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.I0(num1_d[0]),
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.I1(num2_d[0])
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);
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defparam Carry_d_0_s.INIT=4'h8;
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LUT4 Carry_d_1_s (
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.F(Carry_d[1]),
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.I0(num1_d[1]),
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.I1(num2_d[1]),
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.I2(num1_d[0]),
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.I3(num2_d[0])
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);
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defparam Carry_d_1_s.INIT=16'hE888;
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LUT3 sum_d_2_s (
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.F(sum_d[2]),
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.I0(Carry_d[1]),
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.I1(num1_d[2]),
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.I2(num2_d[2])
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);
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defparam sum_d_2_s.INIT=8'h96;
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LUT3 Carry_d_2_s (
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.F(Carry_d[2]),
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.I0(Carry_d[1]),
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.I1(num1_d[2]),
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.I2(num2_d[2])
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);
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defparam Carry_d_2_s.INIT=8'hE8;
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LUT4 sum_d_1_s0 (
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.F(sum_d[1]),
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.I0(num1_d[0]),
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.I1(num2_d[0]),
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.I2(num1_d[1]),
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.I3(num2_d[1])
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);
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defparam sum_d_1_s0.INIT=16'h8778;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* Adder3Bit */
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175
lab3/impl/gwsynthesis/lab3_syn.rpt.html
Normal file
175
lab3/impl/gwsynthesis/lab3_syn.rpt.html
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||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
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||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
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||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
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||||
div#catalog a:hover { color: #fff; background: #0084ff; }
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||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\src\Adder3Bit.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat Apr 13 05:09:20 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>Adder3Bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 156.254MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 156.254MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 156.254MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 156.254MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 156.254MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 156.254MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 156.254MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.301s, Peak memory usage = 172.207MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 172.207MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 172.207MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 172.207MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>12</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>12</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT3</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>6(6 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
46
lab3/impl/gwsynthesis/lab3_syn_resource.html
Normal file
46
lab3/impl/gwsynthesis/lab3_syn_resource.html
Normal file
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">6</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
2
lab3/impl/gwsynthesis/lab3_syn_rsc.xml
Normal file
2
lab3/impl/gwsynthesis/lab3_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="Adder3Bit" Lut="6" T_Lut="6(6)"/>
|
||||
Reference in New Issue
Block a user