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verilog

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k0rrluna
2024-04-13 05:48:55 +03:00
commit ed465dd690
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GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
NOTE (EX0101) : Current top module is "tb"
WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
GowinSynthesis finish

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lab2_prep/impl/gwsynthesis/lab2.prj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\cygwin64\home\koray\verilog\lab2\src\lab2.v" type="verilog"/>
<File path="C:\cygwin64\home\koray\verilog\lab2\src\tb.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

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lab2_prep/impl/gwsynthesis/lab2.vg Normal file
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//
//Written by GowinSynthesis
//Tool Version "V1.9.9.02"
//Thu Apr 11 06:15:18 2024
//Source file index table:
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
`timescale 100 ps/100 ps
module tb (
)
;
wire VCC;
wire GND;
VCC VCC_cZ (
.V(VCC)
);
GND GND_cZ (
.G(GND)
);
GSR GSR (
.GSRI(VCC)
);
endmodule /* tb */

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lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\cygwin64\home\koray\verilog\lab2\src\lab2.v<br>
C:\cygwin64\home\koray\verilog\lab2\src\tb.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Apr 11 06:15:18 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>tb</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>0(0 LUT, 0 ALU) / 20736</td>
<td>0%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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lab2_prep/impl/gwsynthesis/lab2_syn_resource.html Normal file
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Module name="tb"/>