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4-bit ALU

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k0rrluna
2024-12-14 05:00:35 +03:00
parent cd93206ad4
commit cbf97501ea
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project/halfadder.v Normal file
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module halfadder (
input A, B,
output Sum, Carry
);
and a1 (Carry, A, B);
xor xo1 (Sum, A, B);
endmodule