verilog

2024-07-12 23:57:42 +03:00
parent 610e059b8a
commit 997713f8f2
11 changed files with 359 additions and 7 deletions
--- a/gowin/bibp/impl/temp/rtl_parser_arg.json
+++ b/gowin/bibp/impl/temp/rtl_parser_arg.json
@@ -0,0 +1,17 @@
+{
+ "Device" : "GW2A-18C",
+ "Files" : [
+  {
+   "Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/src/bibp.v",
+   "Type" : "verilog"
+  }
+ ],
+ "IncludePath" : [
+
+ ],
+ "LoopLimit" : 2000,
+ "ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/impl/temp/rtl_parser.result",
+ "Top" : "",
+ "VerilogStd" : "verilog_2001",
+ "VhdlStd" : "vhdl_93"
+}