verilog
This commit is contained in:
parent
610e059b8a
commit
997713f8f2
10
gowin/bibp/bibp.gprj
Normal file
10
gowin/bibp/bibp.gprj
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@ -0,0 +1,10 @@
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<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE gowin-fpga-project>
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<Project>
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<Template>FPGA</Template>
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<Version>5</Version>
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<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
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<FileList>
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<File path="src/bibp.v" type="file.verilog" enable="1"/>
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</FileList>
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</Project>
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13
gowin/bibp/bibp.gprj.user
Normal file
13
gowin/bibp/bibp.gprj.user
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@ -0,0 +1,13 @@
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<?xml version="1" encoding="UTF-8"?>
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<!DOCTYPE ProjectUserData>
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<UserConfig>
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<Version>1.0</Version>
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<FlowState>
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<Process ID="Synthesis" State="3"/>
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<Process ID="Pnr" State="0"/>
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<Process ID="Gao" State="0"/>
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<Process ID="Rtl_Gao" State="2"/>
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</FlowState>
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<ResultFileList/>
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<Ui>000000ff00000001fd00000002000000000000018e000003e5fc0200000001fc00000063000003e50000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000ab00000027efc0100000001fc0000000000000ab0000000da00fffffffa000000010100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000009e00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000da00ffffff0000091a000003e500000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000bdffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c007301000001a5ffffffff0000000000000000</Ui>
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</UserConfig>
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88
gowin/bibp/impl/bibp_process_config.json
Normal file
88
gowin/bibp/impl/bibp_process_config.json
Normal file
@ -0,0 +1,88 @@
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{
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"BACKGROUND_PROGRAMMING" : "off",
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"COMPRESS" : false,
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"CPU" : false,
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"CRC_CHECK" : true,
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"Clock_Route_Order" : 0,
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"Correct_Hold_Violation" : true,
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"DONE" : false,
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"DOWNLOAD_SPEED" : "default",
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"Disable_Insert_Pad" : false,
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"ENABLE_CTP" : false,
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"ENABLE_MERGE_MODE" : false,
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||||
"ENCRYPTION_KEY" : false,
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"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
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"ERROR_DECTION_AND_CORRECTION" : false,
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"ERROR_DECTION_ONLY" : false,
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"ERROR_INJECTION" : false,
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"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
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"Enable_DSRM" : false,
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"FORMAT" : "binary",
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"FREQUENCY_DIVIDER" : "",
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"Generate_Constraint_File_of_Ports" : false,
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"Generate_IBIS_File" : false,
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"Generate_Plain_Text_Timing_Report" : false,
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"Generate_Post_PNR_Simulation_Model_File" : false,
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"Generate_Post_Place_File" : false,
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"Generate_SDF_File" : false,
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"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
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"Global_Freq" : "default",
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"GwSyn_Loop_Limit" : 2000,
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"HOTBOOT" : false,
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"I2C" : false,
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"I2C_SLAVE_ADDR" : "00",
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"IncludePath" : [
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],
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"Incremental_Compile" : "",
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"Initialize_Primitives" : false,
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"JTAG" : false,
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"MODE_IO" : false,
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"MSPI" : false,
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"MSPI_JUMP" : false,
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"MULTIBOOT_ADDRESS_WIDTH" : "24",
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"MULTIBOOT_MODE" : "Normal",
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"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
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"MULTIJUMP_ADDRESS_WIDTH" : "24",
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"MULTIJUMP_MODE" : "Normal",
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"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
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"Multi_Boot" : true,
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"OUTPUT_BASE_NAME" : "bibp",
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"POWER_ON_RESET_MONITOR" : true,
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"PRINT_BSRAM_VALUE" : true,
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"PROGRAM_DONE_BYPASS" : false,
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"PlaceInRegToIob" : true,
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"PlaceIoRegToIob" : true,
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"PlaceOutRegToIob" : true,
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"Place_Option" : "0",
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"Process_Configuration_Verion" : "1.0",
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"Promote_Physical_Constraint_Warning_to_Error" : true,
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"READY" : false,
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"RECONFIG_N" : false,
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"Ram_RW_Check" : false,
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"Replicate_Resources" : false,
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"Report_Auto-Placed_Io_Information" : false,
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"Route_Maxfan" : 23,
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"Route_Option" : "0",
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"Run_Timing_Driven" : true,
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"SECURE_MODE" : false,
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"SECURITY_BIT" : true,
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"SEU_HANDLER" : false,
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"SEU_HANDLER_CHECKSUM" : false,
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"SEU_HANDLER_MODE" : "auto",
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"SSPI" : false,
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"STOP_SEU_HANDLER" : false,
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"Show_All_Warnings" : false,
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"Synthesize_tool" : "GowinSyn",
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"TclPre" : "",
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"TopModule" : "",
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"USERCODE" : "default",
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"Unused_Pin" : "As_input_tri_stated_with_pull_up",
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"VCCAUX" : 3.3,
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"VCCX" : "3.3",
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"VHDL_Standard" : "VHDL_Std_1993",
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"Verilog_Standard" : "Vlg_Std_2001",
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"WAKE_UP" : "0",
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"show_all_warnings" : false,
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"turn_off_bg" : false
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}
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14
gowin/bibp/impl/gwsynthesis/bibp.log
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14
gowin/bibp/impl/gwsynthesis/bibp.log
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@ -0,0 +1,14 @@
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v'
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ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":7)
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ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":8)
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ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":12)
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ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":13)
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ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":14)
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ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":15)
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ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":16)
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ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":17)
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ERROR (EX3928) : Module 'bibp' is ignored due to previous errors("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":21)
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Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v' ignored due to errors
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GowinSynthesis finish
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19
gowin/bibp/impl/gwsynthesis/bibp.prj
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19
gowin/bibp/impl/gwsynthesis/bibp.prj
Normal file
@ -0,0 +1,19 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\impl\gwsynthesis\bibp.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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17
gowin/bibp/impl/temp/rtl_parser_arg.json
Normal file
17
gowin/bibp/impl/temp/rtl_parser_arg.json
Normal file
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{
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"Device" : "GW2A-18C",
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"Files" : [
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{
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"Path" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/src/bibp.v",
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"Type" : "verilog"
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}
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],
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"IncludePath" : [
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],
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"LoopLimit" : 2000,
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"ResultFile" : "//wsl.localhost/Debian/home/koray/code/verilog/gowin/bibp/impl/temp/rtl_parser.result",
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"Top" : "",
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"VerilogStd" : "verilog_2001",
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"VhdlStd" : "vhdl_93"
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}
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21
gowin/bibp/src/bibp.v
Normal file
21
gowin/bibp/src/bibp.v
Normal file
@ -0,0 +1,21 @@
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module bibp #(parameter UZUNLUK = 8)(
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input [UZUNLUK + 2:0] buyruk,
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output [UZUNLUK:0] sonuc
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);
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localparam halfUZUNLUK = UZUNLUK / 2;
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localparam v1 = buyruk[UZUNLUK + 2 - 1 : halfUZUNLUK];
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localparam v2 = buyruk[halfUZUNLUK - 1 : 0];
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always@(*) begin
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case(buyruk[UZUNLUK + 2: UZUNLUK -1])
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3'b000: sonuc = v1 + v2;
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3'b001: sonuc = v1 - v2;
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3'b010: sonuc = v1 & v2;
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3'b011: sonuc = v1 | v2;
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3'b100: sonuc = v1 ^ v2;
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default: sonuc = v1 + v2;
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endcase
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end
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endmodule
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@ -1,14 +1,24 @@
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module bibp #(parameter UZUNLUK = 8)(
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input [UZUNLUK + 2:0] buyruk,
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output [UZUNLUK:0] sonuc
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/* output reg [(UZUNLUK/2) - 1:0] v1,
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output reg [(UZUNLUK/2) - 1:0] v2, */
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output reg [(UZUNLUK/2):0] sonuc
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);
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localparam halfUZUNLUK = UZUNLUK/2;
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localparam [halfUZUNLUK - 1 : 0] v1 = buyruk[UZUNLUK - 1: halfUZUNLUK];
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localparam [halfUZUNLUK - 1: 0] v2 = buyruk[halfUZUNLUK - 1 : 0];
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/* localparam halfUZUNLUK = UZUNLUK / 2;
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localparam v1 = buyruk[UZUNLUK - 1 : halfUZUNLUK];
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localparam v2 = buyruk[halfUZUNLUK - 1 : 0];
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*/
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/*assign v1 = buyruk[UZUNLUK - 1 : UZUNLUK/2];
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assign v2 = buyruk[UZUNLUK/2 : 0];*/
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wire [(UZUNLUK/2) - 1:0] v1,v2;
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always@(*) begin
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case(buyruk[UZUNLUK + 2: UZUNLUK -1])
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v1 = buyruk[UZUNLUK - 1 : UZUNLUK/2];
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v2 = buyruk[(UZUNLUK/2) - 1 : 0];
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case(buyruk[UZUNLUK+2:UZUNLUK-1])
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3'b000: sonuc = v1 + v2;
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3'b001: sonuc = v1 - v2;
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3'b010: sonuc = v1 & v2;
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@ -4,13 +4,13 @@ parameter UZUNLUK = 8;
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reg [UZUNLUK+2:0] buyruk;
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wire [UZUNLUK/2:0] sonuc;
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bibp uut(buyruk, sonuc);
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bibp #(.UZUNLUK(UZUNLUK)) uut(.buyruk(buyruk), .sonuc(sonuc));
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initial begin
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$dumpfile("vbibp.vcd");
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$dumpvars;
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buyruk = 11'b000_0101_0101; #10;
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buyruk = 11'b001_0101_0100; #10;
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$finish;
|
||||
end
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endmodule
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34
labs/lab6/vbibp.vcd
Normal file
34
labs/lab6/vbibp.vcd
Normal file
@ -0,0 +1,34 @@
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$date
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||||
Thu Jul 11 19:23:34 2024
|
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$end
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||||
$version
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||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
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||||
$end
|
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$scope module bibpTB $end
|
||||
$var wire 4 ! v2 [3:0] $end
|
||||
$var wire 4 " v1 [3:0] $end
|
||||
$var wire 5 # sonuc [4:0] $end
|
||||
$var reg 11 $ buyruk [10:0] $end
|
||||
$scope module uut $end
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||||
$var wire 11 % buyruk [10:0] $end
|
||||
$var reg 5 & sonuc [4:0] $end
|
||||
$var reg 4 ' v1 [3:0] $end
|
||||
$var reg 4 ( v2 [3:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
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||||
$dumpvars
|
||||
b100 (
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||||
b101 '
|
||||
b100 &
|
||||
b101010100 %
|
||||
b101010100 $
|
||||
b100 #
|
||||
b101 "
|
||||
b100 !
|
||||
$end
|
||||
#10
|
||||
126
labs/lab6/vvbibp
Normal file
126
labs/lab6/vvbibp
Normal file
@ -0,0 +1,126 @@
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#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5634a3f74fe0 .scope module, "bibpTB" "bibpTB" 2 1;
|
||||
.timescale 0 0;
|
||||
P_0x5634a3f60060 .param/l "UZUNLUK" 0 2 3, +C4<00000000000000000000000000001000>;
|
||||
v0x5634a3f87b40_0 .var "buyruk", 10 0;
|
||||
v0x5634a3f87c20_0 .net "sonuc", 4 0, v0x5634a3f877e0_0; 1 drivers
|
||||
v0x5634a3f87cf0_0 .net "v1", 3 0, v0x5634a3f878c0_0; 1 drivers
|
||||
v0x5634a3f87df0_0 .net "v2", 3 0, v0x5634a3f879b0_0; 1 drivers
|
||||
S_0x5634a3f751c0 .scope module, "uut" "bibp" 2 9, 3 1 0, S_0x5634a3f74fe0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 11 "buyruk";
|
||||
.port_info 1 /OUTPUT 4 "v1";
|
||||
.port_info 2 /OUTPUT 4 "v2";
|
||||
.port_info 3 /OUTPUT 5 "sonuc";
|
||||
P_0x5634a3f753a0 .param/l "UZUNLUK" 0 3 1, +C4<00000000000000000000000000001000>;
|
||||
v0x5634a3f38cf0_0 .net "buyruk", 10 0, v0x5634a3f87b40_0; 1 drivers
|
||||
v0x5634a3f877e0_0 .var "sonuc", 4 0;
|
||||
v0x5634a3f878c0_0 .var "v1", 3 0;
|
||||
v0x5634a3f879b0_0 .var "v2", 3 0;
|
||||
E_0x5634a3f39630 .event edge, v0x5634a3f38cf0_0, v0x5634a3f878c0_0, v0x5634a3f879b0_0;
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||||
.scope S_0x5634a3f751c0;
|
||||
T_0 ;
|
||||
%wait E_0x5634a3f39630;
|
||||
%load/vec4 v0x5634a3f38cf0_0;
|
||||
%parti/s 4, 4, 4;
|
||||
%store/vec4 v0x5634a3f878c0_0, 0, 4;
|
||||
%load/vec4 v0x5634a3f38cf0_0;
|
||||
%parti/s 4, 0, 2;
|
||||
%store/vec4 v0x5634a3f879b0_0, 0, 4;
|
||||
%load/vec4 v0x5634a3f38cf0_0;
|
||||
%parti/s 4, 7, 4;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.0, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.1, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.2, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 3, 0, 4;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.3, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 4, 0, 4;
|
||||
%cmp/u;
|
||||
%jmp/1 T_0.4, 6;
|
||||
%load/vec4 v0x5634a3f878c0_0;
|
||||
%pad/u 5;
|
||||
%load/vec4 v0x5634a3f879b0_0;
|
||||
%pad/u 5;
|
||||
%add;
|
||||
%store/vec4 v0x5634a3f877e0_0, 0, 5;
|
||||
%jmp T_0.6;
|
||||
T_0.0 ;
|
||||
%load/vec4 v0x5634a3f878c0_0;
|
||||
%pad/u 5;
|
||||
%load/vec4 v0x5634a3f879b0_0;
|
||||
%pad/u 5;
|
||||
%add;
|
||||
%store/vec4 v0x5634a3f877e0_0, 0, 5;
|
||||
%jmp T_0.6;
|
||||
T_0.1 ;
|
||||
%load/vec4 v0x5634a3f878c0_0;
|
||||
%pad/u 5;
|
||||
%load/vec4 v0x5634a3f879b0_0;
|
||||
%pad/u 5;
|
||||
%sub;
|
||||
%store/vec4 v0x5634a3f877e0_0, 0, 5;
|
||||
%jmp T_0.6;
|
||||
T_0.2 ;
|
||||
%load/vec4 v0x5634a3f878c0_0;
|
||||
%pad/u 5;
|
||||
%load/vec4 v0x5634a3f879b0_0;
|
||||
%pad/u 5;
|
||||
%and;
|
||||
%store/vec4 v0x5634a3f877e0_0, 0, 5;
|
||||
%jmp T_0.6;
|
||||
T_0.3 ;
|
||||
%load/vec4 v0x5634a3f878c0_0;
|
||||
%pad/u 5;
|
||||
%load/vec4 v0x5634a3f879b0_0;
|
||||
%pad/u 5;
|
||||
%or;
|
||||
%store/vec4 v0x5634a3f877e0_0, 0, 5;
|
||||
%jmp T_0.6;
|
||||
T_0.4 ;
|
||||
%load/vec4 v0x5634a3f878c0_0;
|
||||
%pad/u 5;
|
||||
%load/vec4 v0x5634a3f879b0_0;
|
||||
%pad/u 5;
|
||||
%xor;
|
||||
%store/vec4 v0x5634a3f877e0_0, 0, 5;
|
||||
%jmp T_0.6;
|
||||
T_0.6 ;
|
||||
%pop/vec4 1;
|
||||
%jmp T_0;
|
||||
.thread T_0, $push;
|
||||
.scope S_0x5634a3f74fe0;
|
||||
T_1 ;
|
||||
%vpi_call 2 12 "$dumpfile", "vbibp.vcd" {0 0 0};
|
||||
%vpi_call 2 13 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 340, 0, 11;
|
||||
%store/vec4 v0x5634a3f87b40_0, 0, 11;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 16 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_1;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"bibpTB.v";
|
||||
"bibp.v";
|
||||
Loading…
x
Reference in New Issue
Block a user