opCode fixes
This commit is contained in:
parent
0f57860554
commit
8d4ec38521
2258
project/ALU
2258
project/ALU
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
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module ALU (
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input [3:0] A, B,
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input CarryIN,
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input opCodeA, opCodeB, opCodeC,
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input [2:0] opCodeA,
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output [3:0] Y,
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output CarryOUT, overflow
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);
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@ -14,7 +14,7 @@ wire [3:0] resultA, resultO, resultX, lUOutput1;
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wire [3:0] aUtemp1, aUtemp2, lUOutput2;
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wire [3:0] wireY;
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opCode opCd (.A(opCodeA), .B(opCodeB), .C(opCodeC), .opCode(opCode8));
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opCode opCd (.A(opCodeA), .opCode(opCode8));
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arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
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logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
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2620
project/ALU.vcd
2620
project/ALU.vcd
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,7 @@ module ALUTB ();
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reg [3:0] A, B;
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reg CarryIN;
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reg opCodeA, opCodeB, opCodeC;
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reg [2:0] opCodeA;
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wire [3:0] Y;
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wire CarryOUT, overflow;
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@ -11,8 +11,6 @@ ALU uut(
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.B(B),
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.CarryIN(CarryIN),
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.opCodeA(opCodeA),
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.opCodeB(opCodeB),
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.opCodeC(opCodeC),
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.Y(Y),
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.CarryOUT(CarryOUT),
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.overflow(overflow)
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@ -21,17 +19,17 @@ ALU uut(
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initial begin
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$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
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$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
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A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b0; #5;
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
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A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
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A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 1'b0; opCodeB = 1'b0; opCodeC = 1'b1; #5;
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
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A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
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$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
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end
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182
project/opCode
182
project/opCode
@ -7,116 +7,100 @@
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x5607c3854aa0 .scope module, "opCodeTB" "opCodeTB" 2 1;
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S_0x5602ec702f00 .scope module, "opCodeTB" "opCodeTB" 2 1;
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.timescale 0 0;
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v0x5607c386c6f0_0 .var "A", 0 0;
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v0x5607c386c7b0_0 .var "B", 0 0;
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v0x5607c386c880_0 .var "C", 0 0;
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v0x5607c386c980_0 .net "opCode", 7 0, L_0x5607c386d5f0; 1 drivers
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S_0x5607c3854c30 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5607c3854aa0;
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v0x5602ec71a9e0_0 .var "A", 2 0;
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v0x5602ec71aaa0_0 .net "opCode", 7 0, L_0x5602ec71c020; 1 drivers
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S_0x5602ec703090 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5602ec702f00;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "C";
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.port_info 3 /OUTPUT 8 "opCode";
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L_0x5607c386ca50 .functor NOT 1, v0x5607c386c6f0_0, C4<0>, C4<0>, C4<0>;
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L_0x5607c386caf0 .functor NOT 1, v0x5607c386c7b0_0, C4<0>, C4<0>, C4<0>;
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L_0x5607c386cbb0 .functor NOT 1, v0x5607c386c880_0, C4<0>, C4<0>, C4<0>;
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L_0x5607c386cc70 .functor AND 1, v0x5607c386c6f0_0, v0x5607c386c7b0_0, C4<1>, C4<1>;
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L_0x5607c386cd10 .functor AND 1, L_0x5607c386ca50, v0x5607c386c7b0_0, C4<1>, C4<1>;
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L_0x5607c386ce00 .functor AND 1, v0x5607c386c6f0_0, L_0x5607c386caf0, C4<1>, C4<1>;
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L_0x5607c386ceb0 .functor AND 1, L_0x5607c386ca50, L_0x5607c386caf0, C4<1>, C4<1>;
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L_0x5607c386cf20 .functor AND 1, L_0x5607c386ceb0, L_0x5607c386cbb0, C4<1>, C4<1>;
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L_0x5607c386d030 .functor AND 1, L_0x5607c386ceb0, v0x5607c386c880_0, C4<1>, C4<1>;
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L_0x5607c386d0a0 .functor AND 1, L_0x5607c386cd10, L_0x5607c386cbb0, C4<1>, C4<1>;
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L_0x5607c386d1c0 .functor AND 1, L_0x5607c386cd10, v0x5607c386c880_0, C4<1>, C4<1>;
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L_0x5607c386d2c0 .functor AND 1, L_0x5607c386ce00, L_0x5607c386cbb0, C4<1>, C4<1>;
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L_0x5607c386d460 .functor AND 1, L_0x5607c386ce00, v0x5607c386c880_0, C4<1>, C4<1>;
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L_0x5607c386d4d0 .functor AND 1, L_0x5607c386cc70, L_0x5607c386cbb0, C4<1>, C4<1>;
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L_0x5607c386d3f0 .functor AND 1, L_0x5607c386cc70, v0x5607c386c880_0, C4<1>, C4<1>;
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v0x5607c383ff30_0 .net "A", 0 0, v0x5607c386c6f0_0; 1 drivers
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v0x5607c383fae0_0 .net "B", 0 0, v0x5607c386c7b0_0; 1 drivers
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v0x5607c383f690_0 .net "C", 0 0, v0x5607c386c880_0; 1 drivers
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v0x5607c383f240_0 .net *"_ivl_0", 0 0, L_0x5607c386cf20; 1 drivers
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v0x5607c383edf0_0 .net *"_ivl_10", 0 0, L_0x5607c386d460; 1 drivers
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v0x5607c383e970_0 .net *"_ivl_12", 0 0, L_0x5607c386d4d0; 1 drivers
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v0x5607c386bbf0_0 .net *"_ivl_14", 0 0, L_0x5607c386d3f0; 1 drivers
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v0x5607c386bcd0_0 .net *"_ivl_2", 0 0, L_0x5607c386d030; 1 drivers
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v0x5607c386bdb0_0 .net *"_ivl_4", 0 0, L_0x5607c386d0a0; 1 drivers
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v0x5607c386be90_0 .net *"_ivl_6", 0 0, L_0x5607c386d1c0; 1 drivers
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v0x5607c386bf70_0 .net *"_ivl_8", 0 0, L_0x5607c386d2c0; 1 drivers
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v0x5607c386c050_0 .net "and1", 0 0, L_0x5607c386cc70; 1 drivers
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v0x5607c386c110_0 .net "and2", 0 0, L_0x5607c386cd10; 1 drivers
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v0x5607c386c1d0_0 .net "and3", 0 0, L_0x5607c386ce00; 1 drivers
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v0x5607c386c290_0 .net "and4", 0 0, L_0x5607c386ceb0; 1 drivers
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v0x5607c386c350_0 .net "notA", 0 0, L_0x5607c386ca50; 1 drivers
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v0x5607c386c410_0 .net "notB", 0 0, L_0x5607c386caf0; 1 drivers
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v0x5607c386c4d0_0 .net "notC", 0 0, L_0x5607c386cbb0; 1 drivers
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v0x5607c386c590_0 .net "opCode", 7 0, L_0x5607c386d5f0; alias, 1 drivers
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LS_0x5607c386d5f0_0_0 .concat8 [ 1 1 1 1], L_0x5607c386cf20, L_0x5607c386d030, L_0x5607c386d0a0, L_0x5607c386d1c0;
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LS_0x5607c386d5f0_0_4 .concat8 [ 1 1 1 1], L_0x5607c386d2c0, L_0x5607c386d460, L_0x5607c386d4d0, L_0x5607c386d3f0;
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L_0x5607c386d5f0 .concat8 [ 4 4 0 0], LS_0x5607c386d5f0_0_0, LS_0x5607c386d5f0_0_4;
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.scope S_0x5607c3854aa0;
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.port_info 0 /INPUT 3 "A";
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.port_info 1 /OUTPUT 8 "opCode";
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L_0x5602ec71ab70 .functor NOT 1, L_0x5602ec71ac40, C4<0>, C4<0>, C4<0>;
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L_0x5602ec71ad30 .functor NOT 1, L_0x5602ec71adc0, C4<0>, C4<0>, C4<0>;
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L_0x5602ec71aeb0 .functor NOT 1, L_0x5602ec71af50, C4<0>, C4<0>, C4<0>;
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L_0x5602ec71b040 .functor AND 1, L_0x5602ec71b140, L_0x5602ec71b210, C4<1>, C4<1>;
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L_0x5602ec71b300 .functor AND 1, L_0x5602ec71ab70, L_0x5602ec71b3c0, C4<1>, C4<1>;
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L_0x5602ec71b4f0 .functor AND 1, L_0x5602ec71b5f0, L_0x5602ec71ad30, C4<1>, C4<1>;
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L_0x5602ec71b6e0 .functor AND 1, L_0x5602ec71ab70, L_0x5602ec71ad30, C4<1>, C4<1>;
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L_0x5602ec71b750 .functor AND 1, L_0x5602ec71b6e0, L_0x5602ec71aeb0, C4<1>, C4<1>;
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L_0x5602ec71b8b0 .functor AND 1, L_0x5602ec71b6e0, L_0x5602ec71b920, C4<1>, C4<1>;
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L_0x5602ec71ba60 .functor AND 1, L_0x5602ec71b300, L_0x5602ec71aeb0, C4<1>, C4<1>;
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L_0x5602ec71bb80 .functor AND 1, L_0x5602ec71b300, L_0x5602ec71bbf0, C4<1>, C4<1>;
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L_0x5602ec71bc90 .functor AND 1, L_0x5602ec71b4f0, L_0x5602ec71aeb0, C4<1>, C4<1>;
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L_0x5602ec71bdc0 .functor AND 1, L_0x5602ec71b4f0, L_0x5602ec71be30, C4<1>, C4<1>;
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L_0x5602ec71bf30 .functor AND 1, L_0x5602ec71b040, L_0x5602ec71aeb0, C4<1>, C4<1>;
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L_0x5602ec71bd50 .functor AND 1, L_0x5602ec71b040, L_0x5602ec71c3e0, C4<1>, C4<1>;
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v0x5602ec6ef910_0 .net "A", 2 0, v0x5602ec71a9e0_0; 1 drivers
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v0x5602ec6ef0a0_0 .net *"_ivl_1", 0 0, L_0x5602ec71ac40; 1 drivers
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v0x5602ec6eec60_0 .net *"_ivl_11", 0 0, L_0x5602ec71b3c0; 1 drivers
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v0x5602ec6ee3f0_0 .net *"_ivl_13", 0 0, L_0x5602ec71b5f0; 1 drivers
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v0x5602ec6edfc0_0 .net *"_ivl_14", 0 0, L_0x5602ec71b750; 1 drivers
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v0x5602ec719640_0 .net *"_ivl_16", 0 0, L_0x5602ec71b8b0; 1 drivers
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v0x5602ec719720_0 .net *"_ivl_19", 0 0, L_0x5602ec71b920; 1 drivers
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v0x5602ec719800_0 .net *"_ivl_20", 0 0, L_0x5602ec71ba60; 1 drivers
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v0x5602ec7198e0_0 .net *"_ivl_22", 0 0, L_0x5602ec71bb80; 1 drivers
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v0x5602ec7199c0_0 .net *"_ivl_25", 0 0, L_0x5602ec71bbf0; 1 drivers
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v0x5602ec719aa0_0 .net *"_ivl_26", 0 0, L_0x5602ec71bc90; 1 drivers
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v0x5602ec719b80_0 .net *"_ivl_28", 0 0, L_0x5602ec71bdc0; 1 drivers
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v0x5602ec719c60_0 .net *"_ivl_3", 0 0, L_0x5602ec71adc0; 1 drivers
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v0x5602ec719d40_0 .net *"_ivl_31", 0 0, L_0x5602ec71be30; 1 drivers
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v0x5602ec719e20_0 .net *"_ivl_32", 0 0, L_0x5602ec71bf30; 1 drivers
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v0x5602ec719f00_0 .net *"_ivl_34", 0 0, L_0x5602ec71bd50; 1 drivers
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v0x5602ec719fe0_0 .net *"_ivl_38", 0 0, L_0x5602ec71c3e0; 1 drivers
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v0x5602ec71a0c0_0 .net *"_ivl_5", 0 0, L_0x5602ec71af50; 1 drivers
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v0x5602ec71a1a0_0 .net *"_ivl_7", 0 0, L_0x5602ec71b140; 1 drivers
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v0x5602ec71a280_0 .net *"_ivl_9", 0 0, L_0x5602ec71b210; 1 drivers
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v0x5602ec71a360_0 .net "and1", 0 0, L_0x5602ec71b040; 1 drivers
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v0x5602ec71a420_0 .net "and2", 0 0, L_0x5602ec71b300; 1 drivers
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v0x5602ec71a4e0_0 .net "and3", 0 0, L_0x5602ec71b4f0; 1 drivers
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v0x5602ec71a5a0_0 .net "and4", 0 0, L_0x5602ec71b6e0; 1 drivers
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v0x5602ec71a660_0 .net "notA", 0 0, L_0x5602ec71ab70; 1 drivers
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v0x5602ec71a720_0 .net "notB", 0 0, L_0x5602ec71ad30; 1 drivers
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v0x5602ec71a7e0_0 .net "notC", 0 0, L_0x5602ec71aeb0; 1 drivers
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v0x5602ec71a8a0_0 .net "opCode", 7 0, L_0x5602ec71c020; alias, 1 drivers
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L_0x5602ec71ac40 .part v0x5602ec71a9e0_0, 2, 1;
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L_0x5602ec71adc0 .part v0x5602ec71a9e0_0, 1, 1;
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L_0x5602ec71af50 .part v0x5602ec71a9e0_0, 0, 1;
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L_0x5602ec71b140 .part v0x5602ec71a9e0_0, 2, 1;
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L_0x5602ec71b210 .part v0x5602ec71a9e0_0, 1, 1;
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L_0x5602ec71b3c0 .part v0x5602ec71a9e0_0, 1, 1;
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L_0x5602ec71b5f0 .part v0x5602ec71a9e0_0, 2, 1;
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L_0x5602ec71b920 .part v0x5602ec71a9e0_0, 0, 1;
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L_0x5602ec71bbf0 .part v0x5602ec71a9e0_0, 0, 1;
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L_0x5602ec71be30 .part v0x5602ec71a9e0_0, 0, 1;
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LS_0x5602ec71c020_0_0 .concat8 [ 1 1 1 1], L_0x5602ec71b750, L_0x5602ec71b8b0, L_0x5602ec71ba60, L_0x5602ec71bb80;
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LS_0x5602ec71c020_0_4 .concat8 [ 1 1 1 1], L_0x5602ec71bc90, L_0x5602ec71bdc0, L_0x5602ec71bf30, L_0x5602ec71bd50;
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L_0x5602ec71c020 .concat8 [ 4 4 0 0], LS_0x5602ec71c020_0_0, LS_0x5602ec71c020_0_4;
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L_0x5602ec71c3e0 .part v0x5602ec71a9e0_0, 0, 1;
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.scope S_0x5602ec702f00;
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T_0 ;
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%vpi_call 2 14 "$dumpfile", "opCode.vcd" {0 0 0};
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%vpi_call 2 15 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x5607c386c6f0_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x5607c386c7b0_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x5607c386c880_0, 0, 1;
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%vpi_call 2 13 "$dumpfile", "opCode.vcd" {0 0 0};
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%vpi_call 2 14 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 3;
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%store/vec4 v0x5602ec71a9e0_0, 0, 3;
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%delay 3, 0;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x5607c386c6f0_0, 0, 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x5607c386c7b0_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x5607c386c880_0, 0, 1;
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%pushi/vec4 1, 0, 3;
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%store/vec4 v0x5602ec71a9e0_0, 0, 3;
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%delay 3, 0;
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%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c6f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c7b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5607c386c880_0, 0, 1;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%vpi_call 2 24 "$finish" {0 0 0};
|
||||
%vpi_call 2 23 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
|
||||
@ -1,25 +1,25 @@
|
||||
module opCode (
|
||||
input A, B, C,
|
||||
input [2:0] A,
|
||||
output [7:0] opCode
|
||||
);
|
||||
wire and1, and2, and3, and4, notA, notB, notC;
|
||||
|
||||
not n1(notA, A);
|
||||
not n2(notB, B);
|
||||
not n3(notC, C);
|
||||
not n1(notA, A[2]);
|
||||
not n2(notB, A[1]);
|
||||
not n3(notC, A[0]);
|
||||
|
||||
and a01(and1, A, B);
|
||||
and a02(and2, notA, B);
|
||||
and a03(and3, A, notB);
|
||||
and a01(and1, A[2], A[1]);
|
||||
and a02(and2, notA, A[1]);
|
||||
and a03(and3, A[2], notB);
|
||||
and a04(and4, notA, notB);
|
||||
|
||||
and a1(opCode[0], and4, notC);
|
||||
and a2(opCode[1], and4, C);
|
||||
and a2(opCode[1], and4, A[0]);
|
||||
and a3(opCode[2], and2, notC);
|
||||
and a4(opCode[3], and2, C);
|
||||
and a4(opCode[3], and2, A[0]);
|
||||
and a5(opCode[4], and3, notC);
|
||||
and a6(opCode[5], and3, C);
|
||||
and a6(opCode[5], and3, A[0]);
|
||||
and a7(opCode[6], and1, notC);
|
||||
and a8(opCode[7], and1, C);
|
||||
and a8(opCode[7], and1, A[0]);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
$date
|
||||
Sun Dec 15 00:28:47 2024
|
||||
Sun Dec 15 04:12:35 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
@ -9,86 +9,84 @@ $timescale
|
||||
$end
|
||||
$scope module opCodeTB $end
|
||||
$var wire 8 ! opCode [7:0] $end
|
||||
$var reg 1 " A $end
|
||||
$var reg 1 # B $end
|
||||
$var reg 1 $ C $end
|
||||
$var reg 3 " A [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " A $end
|
||||
$var wire 1 # B $end
|
||||
$var wire 1 $ C $end
|
||||
$var wire 1 % and1 $end
|
||||
$var wire 1 & and2 $end
|
||||
$var wire 1 ' and3 $end
|
||||
$var wire 1 ( and4 $end
|
||||
$var wire 1 ) notA $end
|
||||
$var wire 1 * notB $end
|
||||
$var wire 1 + notC $end
|
||||
$var wire 8 , opCode [7:0] $end
|
||||
$var wire 3 # A [2:0] $end
|
||||
$var wire 1 $ and1 $end
|
||||
$var wire 1 % and2 $end
|
||||
$var wire 1 & and3 $end
|
||||
$var wire 1 ' and4 $end
|
||||
$var wire 1 ( notA $end
|
||||
$var wire 1 ) notB $end
|
||||
$var wire 1 * notC $end
|
||||
$var wire 8 + opCode [7:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1 ,
|
||||
1+
|
||||
b1 +
|
||||
1*
|
||||
1)
|
||||
1(
|
||||
0'
|
||||
1'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
b0 #
|
||||
b0 "
|
||||
b1 !
|
||||
$end
|
||||
#3
|
||||
0+
|
||||
b10 !
|
||||
b10 ,
|
||||
1$
|
||||
#6
|
||||
0(
|
||||
1+
|
||||
b100 !
|
||||
b100 ,
|
||||
0*
|
||||
1&
|
||||
0$
|
||||
1#
|
||||
#9
|
||||
0+
|
||||
b1000 !
|
||||
b1000 ,
|
||||
1$
|
||||
#12
|
||||
1'
|
||||
1+
|
||||
b10000 !
|
||||
b10000 ,
|
||||
b10 !
|
||||
b10 +
|
||||
b1 "
|
||||
b1 #
|
||||
#6
|
||||
0'
|
||||
0)
|
||||
1*
|
||||
1%
|
||||
b100 !
|
||||
b100 +
|
||||
b10 "
|
||||
b10 #
|
||||
#9
|
||||
0*
|
||||
b1000 !
|
||||
b1000 +
|
||||
b11 "
|
||||
b11 #
|
||||
#12
|
||||
1&
|
||||
0(
|
||||
1)
|
||||
1*
|
||||
0%
|
||||
b10000 !
|
||||
b10000 +
|
||||
b100 "
|
||||
b100 #
|
||||
#15
|
||||
0*
|
||||
b100000 !
|
||||
b100000 +
|
||||
b101 "
|
||||
b101 #
|
||||
#18
|
||||
0&
|
||||
0)
|
||||
0$
|
||||
0#
|
||||
1"
|
||||
#15
|
||||
0+
|
||||
b100000 !
|
||||
b100000 ,
|
||||
1*
|
||||
1$
|
||||
#18
|
||||
0'
|
||||
1+
|
||||
b1000000 !
|
||||
b1000000 ,
|
||||
0*
|
||||
1%
|
||||
0$
|
||||
1#
|
||||
b1000000 +
|
||||
b110 "
|
||||
b110 #
|
||||
#21
|
||||
0+
|
||||
0*
|
||||
b10000000 !
|
||||
b10000000 ,
|
||||
1$
|
||||
b10000000 +
|
||||
b111 "
|
||||
b111 #
|
||||
#24
|
||||
|
||||
@ -1,26 +1,25 @@
|
||||
module opCodeTB();
|
||||
|
||||
reg A, B, C;
|
||||
reg [2:0] A;
|
||||
wire [7:0] opCode;
|
||||
|
||||
opCode uut (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.C(C),
|
||||
|
||||
.opCode(opCode)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("opCode.vcd");
|
||||
$dumpvars;
|
||||
A = 1'b0; B = 1'b0; C = 1'b0; #3;
|
||||
A = 1'b0; B = 1'b0; C = 1'b1; #3;
|
||||
A = 1'b0; B = 1'b1; C = 1'b0; #3;
|
||||
A = 1'b0; B = 1'b1; C = 1'b1; #3;
|
||||
A = 1'b1; B = 1'b0; C = 1'b0; #3;
|
||||
A = 1'b1; B = 1'b0; C = 1'b1; #3;
|
||||
A = 1'b1; B = 1'b1; C = 1'b0; #3;
|
||||
A = 1'b1; B = 1'b1; C = 1'b1; #3;
|
||||
A = 3'b000; #3;
|
||||
A = 3'b001; #3;
|
||||
A = 3'b010; #3;
|
||||
A = 3'b011; #3;
|
||||
A = 3'b100; #3;
|
||||
A = 3'b101; #3;
|
||||
A = 3'b110; #3;
|
||||
A = 3'b111; #3;
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user