27 lines
348 B
Verilog
27 lines
348 B
Verilog
module opCodeTB();
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reg [2:0] A;
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wire [7:0] opCode;
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opCode uut (
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.A(A),
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.opCode(opCode)
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);
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initial begin
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$dumpfile("opCode.vcd");
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$dumpvars;
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A = 3'b000; #3;
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A = 3'b001; #3;
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A = 3'b010; #3;
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A = 3'b011; #3;
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A = 3'b100; #3;
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A = 3'b101; #3;
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A = 3'b110; #3;
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A = 3'b111; #3;
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$finish;
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end
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endmodule
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