37 lines
1.1 KiB
Verilog
37 lines
1.1 KiB
Verilog
module ALUTB ();
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reg [3:0] A, B;
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reg CarryIN;
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reg [2:0] opCodeA;
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wire [3:0] Y;
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wire CarryOUT, overflow;
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ALU uut(
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.A(A),
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.B(B),
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.CarryIN(CarryIN),
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.opCodeA(opCodeA),
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.Y(Y),
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.CarryOUT(CarryOUT),
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.overflow(overflow)
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);
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initial begin
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$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
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$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
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A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
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A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
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$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
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end
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endmodule
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