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formatter test

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k0rrluna
2024-12-07 05:46:58 +03:00
parent f0551ce34f
commit 6f6f491135
2 changed files with 16 additions and 3 deletions
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6
iverilog/nand2tetris/nands/andGate.v
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@@ -1,7 +1,7 @@
module andGate ( module andGate (
input wire A_i, input wire A_i,
input wire B_i, input wire B_i,
output wire Y_o output wire Y_o
); );
wire nand_out; wire nand_out;

13
iverilog/nand2tetris/nands/andGate.v.orig Normal file
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@@ -0,0 +1,13 @@
module andGate (
input wire A_i,
input wire B_i,
output wire Y_o
);
wire nand_out;
nand nand1 ( nand_out, A_i, B_i );
nand nand2 ( Y_o, nand_out, nand_out );
endmodule