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formatter test

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k0rrluna 2024-12-02 02:42:36 +03:00
parent 1cb96c9f9a
commit f0551ce34f
3 changed files with 45 additions and 43 deletions
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48
iverilog/nand2tetris/nands/andGateTB.v
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@ -1,29 +1,29 @@
module andGateTB ();
reg A, B;
wire Y;
reg A, B;
wire Y;
andGate uut (
.A(A),
.B(B),
.Y(Y)
);
andGate uut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
$dumpfile("andGate.vcd");
$dumpvars;
A = 1'b0;
B = 1'b0;
#10;
A = 1'b0;
B = 1'b1;
#10;
A = 1'b1;
B = 1'b0;
#10;
A = 1'b1;
B = 1'b1;
#10;
$finish;
end
initial begin
$dumpfile("andGate.vcd");
$dumpvars;
A = 1'b0;
B = 1'b0;
#10;
A = 1'b0;
B = 1'b1;
#10;
A = 1'b1;
B = 1'b0;
#10;
A = 1'b1;
B = 1'b1;
#10;
$finish;
end
endmodule

10
iverilog/nand2tetris/nands/notGate.v
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@ -1,5 +1,7 @@
module notGate (input A,
output B);
nand nand1 (B, A, A);
module notGate (
input A,
output B
);
nand nand1 (B, A, A);
endmodule

30
iverilog/nand2tetris/nands/notGateTB.v
View File

@ -1,20 +1,20 @@
module notGateTB ();
reg A;
wire B;
reg A;
wire B;
notGate uut (
.A(A),
.B(B)
);
notGate uut (
.A(A),
.B(B)
);
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A = 1'b0;
#10;
A = 1'b1;
#10;
$finish;
end
initial begin
$dumpfile("notGate.vcd");
$dumpvars;
A = 1'b0;
#10;
A = 1'b1;
#10;
$finish;
end
endmodule