formatter test

2024-12-07 05:46:58 +03:00
parent f0551ce34f
commit 6f6f491135
2 changed files with 16 additions and 3 deletions
--- a/iverilog/nand2tetris/nands/andGate.v
+++ b/iverilog/nand2tetris/nands/andGate.v
@@ -1,7 +1,7 @@
 module andGate (
-    input  wire A_i,
-    input  wire B_i,
-    output wire Y_o
+   input  wire A_i,
+   input  wire B_i,
+   output wire Y_o
 );

   wire nand_out;