kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

verilog

Browse Source
This commit is contained in:
k0rrluna
2024-07-09 20:53:40 +03:00
parent 60e4f65988
commit 610e059b8a
20 changed files with 809 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
labs/lab6/bibp.v Normal file
View File

@ -0,0 +1,21 @@
module bibp #(parameter UZUNLUK = 8)(
input [UZUNLUK + 2:0] buyruk,
output [UZUNLUK:0] sonuc
);
localparam halfUZUNLUK = UZUNLUK/2;
localparam [halfUZUNLUK - 1 : 0] v1 = buyruk[UZUNLUK - 1: halfUZUNLUK];
localparam [halfUZUNLUK - 1: 0] v2 = buyruk[halfUZUNLUK - 1 : 0];
always@(*) begin
case(buyruk[UZUNLUK + 2: UZUNLUK -1])
3'b000: sonuc = v1 + v2;
3'b001: sonuc = v1 - v2;
3'b010: sonuc = v1 & v2;
3'b011: sonuc = v1 | v2;
3'b100: sonuc = v1 ^ v2;
default: sonuc = v1 + v2;
endcase
end
endmodule

16
labs/lab6/bibpTB.v Normal file
View File

@ -0,0 +1,16 @@
module bibpTB();
parameter UZUNLUK = 8;
reg [UZUNLUK+2:0] buyruk;
wire [UZUNLUK/2:0] sonuc;
bibp uut(buyruk, sonuc);
initial begin
$dumpfile("vbibp.vcd");
$dumpvars;
buyruk = 11'b000_0101_0101; #10;
$finish;
end
endmodule