16 lines
242 B
Verilog
16 lines
242 B
Verilog
module bibpTB();
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parameter UZUNLUK = 8;
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reg [UZUNLUK+2:0] buyruk;
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wire [UZUNLUK/2:0] sonuc;
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bibp uut(buyruk, sonuc);
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initial begin
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$dumpfile("vbibp.vcd");
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$dumpvars;
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buyruk = 11'b000_0101_0101; #10;
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$finish;
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end
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endmodule |