verilog
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339ae1f428
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28
labs/lab5/1.v
Normal file
28
labs/lab5/1.v
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module timer (
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input clock,
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input reset,
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input gate,
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input [2:0] counter,
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input way,
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output reg [5:0] count
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);
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reg [5:0] countReg;
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always@(posedge clock or posedge reset) begin
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if (reset) begin
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countReg <= 6'd0;
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end
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else if (gate) begin
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if (way && (countReg != 6'b111_111)) begin
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countReg <= countReg + counter;
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end
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else if (!way && (countReg != 6'b000_000)) begin
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countReg <= countReg - counter;
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end
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end
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end
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assign count = countReg;
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endmodule
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122
labs/lab5/lab5t.vcd
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122
labs/lab5/lab5t.vcd
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$date
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Mon Jul 8 05:12:15 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module timerTB $end
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$var wire 6 ! count [5:0] $end
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$var reg 1 " clock $end
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$var reg 3 # counter [2:0] $end
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$var reg 1 $ gate $end
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$var reg 1 % reset $end
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$var reg 1 & way $end
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$scope module uut $end
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$var wire 1 " clock $end
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$var wire 3 ' counter [2:0] $end
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$var wire 1 $ gate $end
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$var wire 1 % reset $end
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$var wire 1 & way $end
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$var reg 6 ( count [5:0] $end
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$var reg 6 ) countReg [5:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b101011 )
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b101011 (
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b10 '
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1&
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1%
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1$
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b10 #
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0"
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b101011 !
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$end
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#5
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b0 !
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b0 (
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b0 )
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1"
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#10
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0"
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#15
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1"
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#20
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0"
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#25
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1"
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#30
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0"
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#35
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1"
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#40
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0"
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#45
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1"
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#50
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0"
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#55
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1"
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#60
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0"
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#65
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1"
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#70
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0"
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#75
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1"
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#80
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0"
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#85
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1"
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#90
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0"
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#95
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1"
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#100
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0"
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#105
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1"
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#110
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0"
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#115
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1"
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#120
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0"
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#125
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1"
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#130
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0"
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#135
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1"
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#140
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0"
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#145
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1"
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#150
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0"
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#155
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1"
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#160
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0"
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#165
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1"
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#170
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0"
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#175
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1"
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#180
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0"
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#185
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1"
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#190
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0"
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#195
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1"
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#200
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0"
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30
labs/lab5/timer.v
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30
labs/lab5/timer.v
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module timer (
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input clock,
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input reset,
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input gate,
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input [2:0] counter,
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input way,
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output reg [5:0] count
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);
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reg [5:0] countReg = 6'b101_011;
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always@(posedge clock) begin
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if (reset) begin
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countReg <= 6'd0;
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end
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else if (gate) begin
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if (way && (countReg != 6'b111_111)) begin
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countReg <= countReg + counter;
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end
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else if (!way && (countReg != 6'b000_000)) begin
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countReg <= countReg - counter;
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end
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end
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end
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always@(*) begin
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count = countReg;
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end
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endmodule
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27
labs/lab5/timerTB.v
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27
labs/lab5/timerTB.v
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module timerTB ();
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reg clock;
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reg reset;
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reg gate;
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reg [2:0] counter;
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reg way;
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wire [5:0] count;
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timer uut (clock,reset,gate,counter,way,count);
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initial begin
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clock = 0;
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forever begin
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#5 clock = ~clock;
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end
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end
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initial begin
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$dumpfile("lab5t.vcd");
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$dumpvars;
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reset = 1'b0; gate = 1'b1; counter = 3'b010; way = 1'b1;
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#200;
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$finish;
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end
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endmodule
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137
labs/lab5/vlab5
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137
labs/lab5/vlab5
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x55928b0bbf60 .scope module, "timerTB" "timerTB" 2 1;
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.timescale 0 0;
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v0x55928b0d05d0_0 .var "clock", 0 0;
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v0x55928b0d0690_0 .net "count", 5 0, v0x55928b0d0000_0; 1 drivers
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v0x55928b0d0760_0 .var "counter", 2 0;
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v0x55928b0d0860_0 .var "gate", 0 0;
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v0x55928b0d0930_0 .var "reset", 0 0;
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v0x55928b0d0a20_0 .var "way", 0 0;
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S_0x55928b0bc0f0 .scope module, "uut" "timer" 2 9, 3 1 0, S_0x55928b0bbf60;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clock";
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.port_info 1 /INPUT 1 "reset";
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.port_info 2 /INPUT 1 "gate";
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.port_info 3 /INPUT 3 "counter";
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.port_info 4 /INPUT 1 "way";
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.port_info 5 /OUTPUT 6 "count";
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v0x55928b0a8600_0 .net "clock", 0 0, v0x55928b0d05d0_0; 1 drivers
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v0x55928b0d0000_0 .var "count", 5 0;
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v0x55928b0d00e0_0 .var "countReg", 5 0;
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v0x55928b0d01a0_0 .net "counter", 2 0, v0x55928b0d0760_0; 1 drivers
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v0x55928b0d0280_0 .net "gate", 0 0, v0x55928b0d0860_0; 1 drivers
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v0x55928b0d0390_0 .net "reset", 0 0, v0x55928b0d0930_0; 1 drivers
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v0x55928b0d0450_0 .net "way", 0 0, v0x55928b0d0a20_0; 1 drivers
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E_0x55928b0b8e60 .event edge, v0x55928b0d00e0_0;
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E_0x55928b0b9330 .event posedge, v0x55928b0a8600_0;
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.scope S_0x55928b0bc0f0;
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T_0 ;
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%pushi/vec4 43, 0, 6;
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%store/vec4 v0x55928b0d00e0_0, 0, 6;
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%end;
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.thread T_0;
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.scope S_0x55928b0bc0f0;
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T_1 ;
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%wait E_0x55928b0b9330;
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%load/vec4 v0x55928b0d0390_0;
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%flag_set/vec4 8;
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%jmp/0xz T_1.0, 8;
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%pushi/vec4 0, 0, 6;
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%assign/vec4 v0x55928b0d00e0_0, 0;
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%jmp T_1.1;
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T_1.0 ;
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%load/vec4 v0x55928b0d0280_0;
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%flag_set/vec4 8;
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%jmp/0xz T_1.2, 8;
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%load/vec4 v0x55928b0d0450_0;
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%load/vec4 v0x55928b0d00e0_0;
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%pushi/vec4 63, 0, 6;
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%cmp/ne;
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%flag_get/vec4 4;
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%and;
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%flag_set/vec4 8;
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%jmp/0xz T_1.4, 8;
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%load/vec4 v0x55928b0d00e0_0;
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%load/vec4 v0x55928b0d01a0_0;
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%pad/u 6;
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%add;
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%assign/vec4 v0x55928b0d00e0_0, 0;
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%jmp T_1.5;
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T_1.4 ;
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%load/vec4 v0x55928b0d0450_0;
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%nor/r;
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%load/vec4 v0x55928b0d00e0_0;
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%pushi/vec4 0, 0, 6;
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%cmp/ne;
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%flag_get/vec4 4;
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%and;
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%flag_set/vec4 8;
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%jmp/0xz T_1.6, 8;
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%load/vec4 v0x55928b0d00e0_0;
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%load/vec4 v0x55928b0d01a0_0;
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%pad/u 6;
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%sub;
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%assign/vec4 v0x55928b0d00e0_0, 0;
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T_1.6 ;
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T_1.5 ;
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T_1.2 ;
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T_1.1 ;
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%jmp T_1;
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.thread T_1;
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.scope S_0x55928b0bc0f0;
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T_2 ;
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%wait E_0x55928b0b8e60;
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%load/vec4 v0x55928b0d00e0_0;
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%store/vec4 v0x55928b0d0000_0, 0, 6;
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%jmp T_2;
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.thread T_2, $push;
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.scope S_0x55928b0bbf60;
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T_3 ;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x55928b0d05d0_0, 0, 1;
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T_3.0 ;
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%delay 5, 0;
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%load/vec4 v0x55928b0d05d0_0;
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%inv;
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%store/vec4 v0x55928b0d05d0_0, 0, 1;
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%jmp T_3.0;
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%end;
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.thread T_3;
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.scope S_0x55928b0bbf60;
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T_4 ;
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%vpi_call 2 19 "$dumpfile", "lab5t.vcd" {0 0 0};
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%vpi_call 2 20 "$dumpvars" {0 0 0};
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x55928b0d0930_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x55928b0d0860_0, 0, 1;
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%pushi/vec4 2, 0, 3;
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%store/vec4 v0x55928b0d0760_0, 0, 3;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x55928b0d0a20_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x55928b0d0930_0, 0, 1;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x55928b0d0860_0, 0, 1;
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%pushi/vec4 2, 0, 3;
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%store/vec4 v0x55928b0d0760_0, 0, 3;
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x55928b0d0a20_0, 0, 1;
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%delay 200, 0;
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%vpi_call 2 25 "$finish" {0 0 0};
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%end;
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.thread T_4;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"timerTB.v";
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"timer.v";
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