27 lines
414 B
Verilog
27 lines
414 B
Verilog
module timerTB ();
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reg clock;
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reg reset;
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reg gate;
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reg [2:0] counter;
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reg way;
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wire [5:0] count;
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timer uut (clock,reset,gate,counter,way,count);
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initial begin
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clock = 0;
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forever begin
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#5 clock = ~clock;
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end
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end
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initial begin
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$dumpfile("lab5t.vcd");
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$dumpvars;
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reset = 1'b0; gate = 1'b1; counter = 3'b010; way = 1'b1;
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#200;
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$finish;
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end
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endmodule |