From 60e4f65988b4cee8abc5b1f365d2c213a88ddd8a Mon Sep 17 00:00:00 2001 From: k0rrluna Date: Mon, 8 Jul 2024 05:13:47 +0300 Subject: [PATCH] verilog --- labs/lab5/1.v | 28 +++++++++ labs/lab5/lab5t.vcd | 122 +++++++++++++++++++++++++++++++++++++++ labs/lab5/timer.v | 30 ++++++++++ labs/lab5/timerTB.v | 27 +++++++++ labs/lab5/vlab5 | 137 ++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 344 insertions(+) create mode 100644 labs/lab5/1.v create mode 100644 labs/lab5/lab5t.vcd create mode 100644 labs/lab5/timer.v create mode 100644 labs/lab5/timerTB.v create mode 100644 labs/lab5/vlab5 diff --git a/labs/lab5/1.v b/labs/lab5/1.v new file mode 100644 index 0000000..3e29f76 --- /dev/null +++ b/labs/lab5/1.v @@ -0,0 +1,28 @@ +module timer ( + input clock, + input reset, + input gate, + input [2:0] counter, + input way, + output reg [5:0] count +); +reg [5:0] countReg; + + +always@(posedge clock or posedge reset) begin + if (reset) begin + countReg <= 6'd0; + end + else if (gate) begin + if (way && (countReg != 6'b111_111)) begin + countReg <= countReg + counter; + end + else if (!way && (countReg != 6'b000_000)) begin + countReg <= countReg - counter; + end + end +end + +assign count = countReg; + +endmodule \ No newline at end of file diff --git a/labs/lab5/lab5t.vcd b/labs/lab5/lab5t.vcd new file mode 100644 index 0000000..21e2e12 --- /dev/null +++ b/labs/lab5/lab5t.vcd @@ -0,0 +1,122 @@ +$date + Mon Jul 8 05:12:15 2024 +$end +$version + Icarus Verilog +$end +$timescale + 1s +$end +$scope module timerTB $end +$var wire 6 ! count [5:0] $end +$var reg 1 " clock $end +$var reg 3 # counter [2:0] $end +$var reg 1 $ gate $end +$var reg 1 % reset $end +$var reg 1 & way $end +$scope module uut $end +$var wire 1 " clock $end +$var wire 3 ' counter [2:0] $end +$var wire 1 $ gate $end +$var wire 1 % reset $end +$var wire 1 & way $end +$var reg 6 ( count [5:0] $end +$var reg 6 ) countReg [5:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b101011 ) +b101011 ( +b10 ' +1& +1% +1$ +b10 # +0" +b101011 ! +$end +#5 +b0 ! +b0 ( +b0 ) +1" +#10 +0" +#15 +1" +#20 +0" +#25 +1" +#30 +0" +#35 +1" +#40 +0" +#45 +1" +#50 +0" +#55 +1" +#60 +0" +#65 +1" +#70 +0" +#75 +1" +#80 +0" +#85 +1" +#90 +0" +#95 +1" +#100 +0" +#105 +1" +#110 +0" +#115 +1" +#120 +0" +#125 +1" +#130 +0" +#135 +1" +#140 +0" +#145 +1" +#150 +0" +#155 +1" +#160 +0" +#165 +1" +#170 +0" +#175 +1" +#180 +0" +#185 +1" +#190 +0" +#195 +1" +#200 +0" diff --git a/labs/lab5/timer.v b/labs/lab5/timer.v new file mode 100644 index 0000000..c77d490 --- /dev/null +++ b/labs/lab5/timer.v @@ -0,0 +1,30 @@ +module timer ( + input clock, + input reset, + input gate, + input [2:0] counter, + input way, + output reg [5:0] count +); +reg [5:0] countReg = 6'b101_011; + + +always@(posedge clock) begin + if (reset) begin + countReg <= 6'd0; + end + else if (gate) begin + if (way && (countReg != 6'b111_111)) begin + countReg <= countReg + counter; + end + else if (!way && (countReg != 6'b000_000)) begin + countReg <= countReg - counter; + end + end +end + +always@(*) begin + count = countReg; +end + +endmodule \ No newline at end of file diff --git a/labs/lab5/timerTB.v b/labs/lab5/timerTB.v new file mode 100644 index 0000000..8e6a2bb --- /dev/null +++ b/labs/lab5/timerTB.v @@ -0,0 +1,27 @@ +module timerTB (); + reg clock; + reg reset; + reg gate; + reg [2:0] counter; + reg way; + wire [5:0] count; + +timer uut (clock,reset,gate,counter,way,count); + +initial begin + clock = 0; + forever begin + #5 clock = ~clock; + end +end + +initial begin + $dumpfile("lab5t.vcd"); + $dumpvars; + + reset = 1'b0; gate = 1'b1; counter = 3'b010; way = 1'b1; + #200; + $finish; +end + +endmodule \ No newline at end of file diff --git a/labs/lab5/vlab5 b/labs/lab5/vlab5 new file mode 100644 index 0000000..4fd8844 --- /dev/null +++ b/labs/lab5/vlab5 @@ -0,0 +1,137 @@ +#! /usr/bin/vvp +:ivl_version "11.0 (stable)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision + 0; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi"; +:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi"; +S_0x55928b0bbf60 .scope module, "timerTB" "timerTB" 2 1; + .timescale 0 0; +v0x55928b0d05d0_0 .var "clock", 0 0; +v0x55928b0d0690_0 .net "count", 5 0, v0x55928b0d0000_0; 1 drivers +v0x55928b0d0760_0 .var "counter", 2 0; +v0x55928b0d0860_0 .var "gate", 0 0; +v0x55928b0d0930_0 .var "reset", 0 0; +v0x55928b0d0a20_0 .var "way", 0 0; +S_0x55928b0bc0f0 .scope module, "uut" "timer" 2 9, 3 1 0, S_0x55928b0bbf60; + .timescale 0 0; + .port_info 0 /INPUT 1 "clock"; + .port_info 1 /INPUT 1 "reset"; + .port_info 2 /INPUT 1 "gate"; + .port_info 3 /INPUT 3 "counter"; + .port_info 4 /INPUT 1 "way"; + .port_info 5 /OUTPUT 6 "count"; +v0x55928b0a8600_0 .net "clock", 0 0, v0x55928b0d05d0_0; 1 drivers +v0x55928b0d0000_0 .var "count", 5 0; +v0x55928b0d00e0_0 .var "countReg", 5 0; +v0x55928b0d01a0_0 .net "counter", 2 0, v0x55928b0d0760_0; 1 drivers +v0x55928b0d0280_0 .net "gate", 0 0, v0x55928b0d0860_0; 1 drivers +v0x55928b0d0390_0 .net "reset", 0 0, v0x55928b0d0930_0; 1 drivers +v0x55928b0d0450_0 .net "way", 0 0, v0x55928b0d0a20_0; 1 drivers +E_0x55928b0b8e60 .event edge, v0x55928b0d00e0_0; +E_0x55928b0b9330 .event posedge, v0x55928b0a8600_0; + .scope S_0x55928b0bc0f0; +T_0 ; + %pushi/vec4 43, 0, 6; + %store/vec4 v0x55928b0d00e0_0, 0, 6; + %end; + .thread T_0; + .scope S_0x55928b0bc0f0; +T_1 ; + %wait E_0x55928b0b9330; + %load/vec4 v0x55928b0d0390_0; + %flag_set/vec4 8; + %jmp/0xz T_1.0, 8; + %pushi/vec4 0, 0, 6; + %assign/vec4 v0x55928b0d00e0_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0x55928b0d0280_0; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %load/vec4 v0x55928b0d0450_0; + %load/vec4 v0x55928b0d00e0_0; + %pushi/vec4 63, 0, 6; + %cmp/ne; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.4, 8; + %load/vec4 v0x55928b0d00e0_0; + %load/vec4 v0x55928b0d01a0_0; + %pad/u 6; + %add; + %assign/vec4 v0x55928b0d00e0_0, 0; + %jmp T_1.5; +T_1.4 ; + %load/vec4 v0x55928b0d0450_0; + %nor/r; + %load/vec4 v0x55928b0d00e0_0; + %pushi/vec4 0, 0, 6; + %cmp/ne; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.6, 8; + %load/vec4 v0x55928b0d00e0_0; + %load/vec4 v0x55928b0d01a0_0; + %pad/u 6; + %sub; + %assign/vec4 v0x55928b0d00e0_0, 0; +T_1.6 ; +T_1.5 ; +T_1.2 ; +T_1.1 ; + %jmp T_1; + .thread T_1; + .scope S_0x55928b0bc0f0; +T_2 ; + %wait E_0x55928b0b8e60; + %load/vec4 v0x55928b0d00e0_0; + %store/vec4 v0x55928b0d0000_0, 0, 6; + %jmp T_2; + .thread T_2, $push; + .scope S_0x55928b0bbf60; +T_3 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55928b0d05d0_0, 0, 1; +T_3.0 ; + %delay 5, 0; + %load/vec4 v0x55928b0d05d0_0; + %inv; + %store/vec4 v0x55928b0d05d0_0, 0, 1; + %jmp T_3.0; + %end; + .thread T_3; + .scope S_0x55928b0bbf60; +T_4 ; + %vpi_call 2 19 "$dumpfile", "lab5t.vcd" {0 0 0}; + %vpi_call 2 20 "$dumpvars" {0 0 0}; + %pushi/vec4 0, 0, 1; + %store/vec4 v0x55928b0d0930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55928b0d0860_0, 0, 1; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x55928b0d0760_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55928b0d0a20_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55928b0d0930_0, 0, 1; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55928b0d0860_0, 0, 1; + %pushi/vec4 2, 0, 3; + %store/vec4 v0x55928b0d0760_0, 0, 3; + %pushi/vec4 1, 0, 1; + %store/vec4 v0x55928b0d0a20_0, 0, 1; + %delay 200, 0; + %vpi_call 2 25 "$finish" {0 0 0}; + %end; + .thread T_4; +# The file index is used to find the file name in the following table. +:file_names 4; + "N/A"; + ""; + "timerTB.v"; + "timer.v";