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verilog

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kaltinsoy committed 2024-05-07 16:15:21 +03:00
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commit 492a55d360
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lab3/impl/gwsynthesis/lab3_syn_resource.html
+22 -2
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@@ -30,10 +30,30 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">6</td>
<td align = "center">1</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--h0
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">1</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--h1
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">2</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>