some random things
This commit is contained in:
parent
ceede4abc3
commit
39d8168cc0
32
project0.2/PU.v
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32
project0.2/PU.v
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module PU (
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input A, // Dividend bit
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input B, // Divisor bit
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input Cin, // Carry input
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input S, // Select input for the mux
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output Y, // Output of the PU
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output COut // Carry output from the full adder
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);
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wire Sum, notB;
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// Invert B for subtraction
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not n1 (notB, B);
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// Full adder performs A - B + Cin
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fulladder f1 (
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.A(A),
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.B(notB),
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.Carry(Cin),
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.Sum(Sum),
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.CarryO(COut)
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);
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// 2:1 multiplexer to select between A and Sum
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mux2 m1 (
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.A0(A), // Input 0 of mux
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.A1(Sum), // Input 1 of mux
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.S(S), // Select line
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.Y(Y) // Output of the mux
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);
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endmodule
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11
project0.2/divider.v
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11
project0.2/divider.v
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module divider (
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input [3:0] D,
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input [1:0] d,
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output [2:0] R,
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output [3:0] Q
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);
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wire s1,y1,c1;
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dividerpu d1 (.A(D[3]), .B(d[0]), .Cin(1'b1), .S(s1), .Y(y1), .COut(c1));
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dividerpu d2 (.A(1'b0), .B(d[1]), .Cin(c1), .S(s1), .Y(y1), .COut(c1));
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391
project0.2/divider4
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391
project0.2/divider4
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@ -0,0 +1,391 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x55ec337fbbf0 .scope module, "divider4TB" "divider4TB" 2 1;
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.timescale 0 0;
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v0x55ec33821ff0_0 .var "Dividend", 3 0;
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v0x55ec338220d0_0 .var "Divisor", 1 0;
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v0x55ec33822170_0 .net "Quotient", 3 0, L_0x55ec338251a0; 1 drivers
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v0x55ec33822240_0 .net "Remainder", 2 0, L_0x55ec33825510; 1 drivers
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S_0x55ec337fa3a0 .scope module, "uut" "divider4" 2 12, 3 1 0, S_0x55ec337fbbf0;
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.timescale 0 0;
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.port_info 0 /INPUT 4 "Dividend";
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.port_info 1 /INPUT 2 "Divisor";
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.port_info 2 /OUTPUT 4 "Quotient";
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.port_info 3 /OUTPUT 3 "Remainder";
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L_0x55ec338251a0 .functor BUFZ 4, L_0x55ec338252b0, C4<0000>, C4<0000>, C4<0000>;
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v0x55ec338218a0_0 .net "Carry", 3 0, L_0x55ec338253d0; 1 drivers
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v0x55ec338219a0_0 .net "Dividend", 3 0, v0x55ec33821ff0_0; 1 drivers
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v0x55ec33821a80_0 .net "Divisor", 1 0, v0x55ec338220d0_0; 1 drivers
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v0x55ec33821b40_0 .net "Quotient", 3 0, L_0x55ec338251a0; alias, 1 drivers
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v0x55ec33821c20_0 .net "Remainder", 2 0, L_0x55ec33825510; alias, 1 drivers
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v0x55ec33821d50_0 .net "S0", 0 0, L_0x55ec33822310; 1 drivers
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v0x55ec33821df0_0 .net "S1", 0 0, L_0x55ec338223e0; 1 drivers
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v0x55ec33821e90_0 .net "Y", 3 0, L_0x55ec338252b0; 1 drivers
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L_0x55ec33822310 .part L_0x55ec338253d0, 3, 1;
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L_0x55ec338223e0 .part L_0x55ec338253d0, 2, 1;
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L_0x55ec33822d50 .part v0x55ec33821ff0_0, 3, 1;
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L_0x55ec33822e40 .part v0x55ec338220d0_0, 1, 1;
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L_0x55ec338238c0 .part v0x55ec33821ff0_0, 2, 1;
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L_0x55ec33823960 .part v0x55ec338220d0_0, 1, 1;
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L_0x55ec33823a90 .part L_0x55ec338253d0, 3, 1;
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L_0x55ec338243b0 .part v0x55ec33821ff0_0, 1, 1;
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L_0x55ec33824530 .part v0x55ec338220d0_0, 0, 1;
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L_0x55ec33824660 .part L_0x55ec338253d0, 2, 1;
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L_0x55ec33825060 .part v0x55ec33821ff0_0, 0, 1;
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L_0x55ec33825100 .part v0x55ec338220d0_0, 0, 1;
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L_0x55ec33825210 .part L_0x55ec338253d0, 1, 1;
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L_0x55ec338252b0 .concat8 [ 1 1 1 1], L_0x55ec33824ff0, L_0x55ec338242f0, L_0x55ec33823800, L_0x55ec33822c60;
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L_0x55ec338253d0 .concat8 [ 1 1 1 1], L_0x55ec33824db0, L_0x55ec338240b0, L_0x55ec338235c0, L_0x55ec33822a20;
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L_0x55ec33825510 .part L_0x55ec338253d0, 0, 3;
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S_0x55ec337f9f60 .scope module, "PU1" "PU" 3 17, 4 1 0, S_0x55ec337fa3a0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Cin";
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.port_info 3 /INPUT 1 "S";
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.port_info 4 /OUTPUT 1 "Y";
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.port_info 5 /OUTPUT 1 "COut";
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L_0x55ec33822480 .functor NOT 1, L_0x55ec33822e40, C4<0>, C4<0>, C4<0>;
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v0x55ec33819cb0_0 .net "A", 0 0, L_0x55ec33822d50; 1 drivers
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v0x55ec33819d70_0 .net "B", 0 0, L_0x55ec33822e40; 1 drivers
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v0x55ec33819e30_0 .net "COut", 0 0, L_0x55ec33822a20; 1 drivers
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L_0x7f82dfd33018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
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v0x55ec33819ed0_0 .net "Cin", 0 0, L_0x7f82dfd33018; 1 drivers
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v0x55ec33819fc0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec3381a0b0_0 .net "Sum", 0 0, L_0x55ec33822870; 1 drivers
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v0x55ec3381a150_0 .net "Y", 0 0, L_0x55ec33822c60; 1 drivers
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v0x55ec3381a1f0_0 .net "notB", 0 0, L_0x55ec33822480; 1 drivers
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S_0x55ec337f9a30 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec337f9f60;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Carry";
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.port_info 3 /OUTPUT 1 "Sum";
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.port_info 4 /OUTPUT 1 "CarryO";
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L_0x55ec33822a20 .functor OR 1, L_0x55ec338224f0, L_0x55ec33822730, C4<0>, C4<0>;
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v0x55ec33818dd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
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v0x55ec33818e90_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
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v0x55ec33818f60_0 .net "Carry", 0 0, L_0x7f82dfd33018; alias, 1 drivers
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v0x55ec33819060_0 .net "CarryO", 0 0, L_0x55ec33822a20; alias, 1 drivers
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v0x55ec33819100_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
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v0x55ec338191f0_0 .net "and1", 0 0, L_0x55ec338224f0; 1 drivers
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v0x55ec338192c0_0 .net "and2", 0 0, L_0x55ec33822730; 1 drivers
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v0x55ec33819390_0 .net "xor1", 0 0, L_0x55ec338226a0; 1 drivers
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S_0x55ec337f7800 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec337f9a30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec338224f0 .functor AND 1, L_0x55ec33822d50, L_0x55ec33822480, C4<1>, C4<1>;
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L_0x55ec338226a0 .functor XOR 1, L_0x55ec33822d50, L_0x55ec33822480, C4<0>, C4<0>;
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v0x55ec337f5bd0_0 .net "A", 0 0, L_0x55ec33822d50; alias, 1 drivers
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v0x55ec337f7e00_0 .net "B", 0 0, L_0x55ec33822480; alias, 1 drivers
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v0x55ec337f36f0_0 .net "Carry", 0 0, L_0x55ec338224f0; alias, 1 drivers
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v0x55ec337f5980_0 .net "Sum", 0 0, L_0x55ec338226a0; alias, 1 drivers
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S_0x55ec33818960 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec337f9a30;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec33822730 .functor AND 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<1>, C4<1>;
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L_0x55ec33822870 .functor XOR 1, L_0x55ec338226a0, L_0x7f82dfd33018, C4<0>, C4<0>;
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v0x55ec337f7bb0_0 .net "A", 0 0, L_0x55ec338226a0; alias, 1 drivers
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v0x55ec337f9de0_0 .net "B", 0 0, L_0x7f82dfd33018; alias, 1 drivers
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v0x55ec33818b90_0 .net "Carry", 0 0, L_0x55ec33822730; alias, 1 drivers
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v0x55ec33818c60_0 .net "Sum", 0 0, L_0x55ec33822870; alias, 1 drivers
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S_0x55ec33819480 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec337f9f60;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A0";
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.port_info 1 /INPUT 1 "A1";
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.port_info 2 /INPUT 1 "S";
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.port_info 3 /OUTPUT 1 "Y";
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L_0x55ec33822ad0 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
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L_0x55ec33822b60 .functor AND 1, L_0x55ec33822870, L_0x55ec33822310, C4<1>, C4<1>;
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L_0x55ec33822bf0 .functor AND 1, L_0x55ec33822ad0, L_0x55ec33822d50, C4<1>, C4<1>;
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L_0x55ec33822c60 .functor OR 1, L_0x55ec33822b60, L_0x55ec33822bf0, C4<0>, C4<0>;
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v0x55ec33819660_0 .net "A0", 0 0, L_0x55ec33822d50; alias, 1 drivers
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v0x55ec33819750_0 .net "A1", 0 0, L_0x55ec33822870; alias, 1 drivers
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v0x55ec33819860_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec33819900_0 .net "Y", 0 0, L_0x55ec33822c60; alias, 1 drivers
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v0x55ec338199a0_0 .net "and1", 0 0, L_0x55ec33822b60; 1 drivers
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v0x55ec33819ab0_0 .net "and2", 0 0, L_0x55ec33822bf0; 1 drivers
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v0x55ec33819b70_0 .net "notS", 0 0, L_0x55ec33822ad0; 1 drivers
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S_0x55ec3381a320 .scope module, "PU2" "PU" 3 26, 4 1 0, S_0x55ec337fa3a0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Cin";
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.port_info 3 /INPUT 1 "S";
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.port_info 4 /OUTPUT 1 "Y";
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.port_info 5 /OUTPUT 1 "COut";
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L_0x55ec33822fb0 .functor NOT 1, L_0x55ec33823960, C4<0>, C4<0>, C4<0>;
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v0x55ec3381c350_0 .net "A", 0 0, L_0x55ec338238c0; 1 drivers
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v0x55ec3381c410_0 .net "B", 0 0, L_0x55ec33823960; 1 drivers
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v0x55ec3381c4d0_0 .net "COut", 0 0, L_0x55ec338235c0; 1 drivers
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v0x55ec3381c570_0 .net "Cin", 0 0, L_0x55ec33823a90; 1 drivers
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v0x55ec3381c660_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
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v0x55ec3381c750_0 .net "Sum", 0 0, L_0x55ec33823410; 1 drivers
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v0x55ec3381c7f0_0 .net "Y", 0 0, L_0x55ec33823800; 1 drivers
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v0x55ec3381c890_0 .net "notB", 0 0, L_0x55ec33822fb0; 1 drivers
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S_0x55ec3381a5c0 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381a320;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Carry";
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.port_info 3 /OUTPUT 1 "Sum";
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.port_info 4 /OUTPUT 1 "CarryO";
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L_0x55ec338235c0 .functor OR 1, L_0x55ec33823020, L_0x55ec338232d0, C4<0>, C4<0>;
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v0x55ec3381b3d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
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v0x55ec3381b490_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
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v0x55ec3381b560_0 .net "Carry", 0 0, L_0x55ec33823a90; alias, 1 drivers
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v0x55ec3381b660_0 .net "CarryO", 0 0, L_0x55ec338235c0; alias, 1 drivers
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v0x55ec3381b700_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
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v0x55ec3381b7f0_0 .net "and1", 0 0, L_0x55ec33823020; 1 drivers
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v0x55ec3381b8c0_0 .net "and2", 0 0, L_0x55ec338232d0; 1 drivers
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v0x55ec3381b990_0 .net "xor1", 0 0, L_0x55ec33823240; 1 drivers
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S_0x55ec3381a7a0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381a5c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec33823020 .functor AND 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<1>, C4<1>;
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L_0x55ec33823240 .functor XOR 1, L_0x55ec338238c0, L_0x55ec33822fb0, C4<0>, C4<0>;
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v0x55ec3381a9d0_0 .net "A", 0 0, L_0x55ec338238c0; alias, 1 drivers
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v0x55ec3381aab0_0 .net "B", 0 0, L_0x55ec33822fb0; alias, 1 drivers
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v0x55ec3381ab70_0 .net "Carry", 0 0, L_0x55ec33823020; alias, 1 drivers
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v0x55ec3381ac40_0 .net "Sum", 0 0, L_0x55ec33823240; alias, 1 drivers
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S_0x55ec3381adb0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381a5c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "Sum";
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.port_info 3 /OUTPUT 1 "Carry";
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L_0x55ec338232d0 .functor AND 1, L_0x55ec33823240, L_0x55ec33823a90, C4<1>, C4<1>;
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L_0x55ec33823410 .functor XOR 1, L_0x55ec33823240, L_0x55ec33823a90, C4<0>, C4<0>;
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v0x55ec3381b020_0 .net "A", 0 0, L_0x55ec33823240; alias, 1 drivers
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v0x55ec3381b0f0_0 .net "B", 0 0, L_0x55ec33823a90; alias, 1 drivers
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v0x55ec3381b190_0 .net "Carry", 0 0, L_0x55ec338232d0; alias, 1 drivers
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||||||
|
v0x55ec3381b260_0 .net "Sum", 0 0, L_0x55ec33823410; alias, 1 drivers
|
||||||
|
S_0x55ec3381ba80 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381a320;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A0";
|
||||||
|
.port_info 1 /INPUT 1 "A1";
|
||||||
|
.port_info 2 /INPUT 1 "S";
|
||||||
|
.port_info 3 /OUTPUT 1 "Y";
|
||||||
|
L_0x55ec33823670 .functor NOT 1, L_0x55ec33822310, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x55ec33823700 .functor AND 1, L_0x55ec33823410, L_0x55ec33822310, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33823790 .functor AND 1, L_0x55ec33823670, L_0x55ec338238c0, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33823800 .functor OR 1, L_0x55ec33823700, L_0x55ec33823790, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381bcd0_0 .net "A0", 0 0, L_0x55ec338238c0; alias, 1 drivers
|
||||||
|
v0x55ec3381bdc0_0 .net "A1", 0 0, L_0x55ec33823410; alias, 1 drivers
|
||||||
|
v0x55ec3381bed0_0 .net "S", 0 0, L_0x55ec33822310; alias, 1 drivers
|
||||||
|
v0x55ec3381bfc0_0 .net "Y", 0 0, L_0x55ec33823800; alias, 1 drivers
|
||||||
|
v0x55ec3381c060_0 .net "and1", 0 0, L_0x55ec33823700; 1 drivers
|
||||||
|
v0x55ec3381c150_0 .net "and2", 0 0, L_0x55ec33823790; 1 drivers
|
||||||
|
v0x55ec3381c210_0 .net "notS", 0 0, L_0x55ec33823670; 1 drivers
|
||||||
|
S_0x55ec3381c9e0 .scope module, "PU3" "PU" 3 36, 4 1 0, S_0x55ec337fa3a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Cin";
|
||||||
|
.port_info 3 /INPUT 1 "S";
|
||||||
|
.port_info 4 /OUTPUT 1 "Y";
|
||||||
|
.port_info 5 /OUTPUT 1 "COut";
|
||||||
|
L_0x55ec33823b30 .functor NOT 1, L_0x55ec33824530, C4<0>, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381ea80_0 .net "A", 0 0, L_0x55ec338243b0; 1 drivers
|
||||||
|
v0x55ec3381eb40_0 .net "B", 0 0, L_0x55ec33824530; 1 drivers
|
||||||
|
v0x55ec3381ec00_0 .net "COut", 0 0, L_0x55ec338240b0; 1 drivers
|
||||||
|
v0x55ec3381eca0_0 .net "Cin", 0 0, L_0x55ec33824660; 1 drivers
|
||||||
|
v0x55ec3381ed90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||||
|
v0x55ec3381ee80_0 .net "Sum", 0 0, L_0x55ec33823f00; 1 drivers
|
||||||
|
v0x55ec3381ef20_0 .net "Y", 0 0, L_0x55ec338242f0; 1 drivers
|
||||||
|
v0x55ec3381efc0_0 .net "notB", 0 0, L_0x55ec33823b30; 1 drivers
|
||||||
|
S_0x55ec3381cc60 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381c9e0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x55ec338240b0 .functor OR 1, L_0x55ec33823ba0, L_0x55ec33823dc0, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381db30_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
|
||||||
|
v0x55ec3381dbf0_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
|
||||||
|
v0x55ec3381dcc0_0 .net "Carry", 0 0, L_0x55ec33824660; alias, 1 drivers
|
||||||
|
v0x55ec3381ddc0_0 .net "CarryO", 0 0, L_0x55ec338240b0; alias, 1 drivers
|
||||||
|
v0x55ec3381de60_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
|
||||||
|
v0x55ec3381df50_0 .net "and1", 0 0, L_0x55ec33823ba0; 1 drivers
|
||||||
|
v0x55ec3381e020_0 .net "and2", 0 0, L_0x55ec33823dc0; 1 drivers
|
||||||
|
v0x55ec3381e0f0_0 .net "xor1", 0 0, L_0x55ec33823d30; 1 drivers
|
||||||
|
S_0x55ec3381cec0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381cc60;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x55ec33823ba0 .functor AND 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33823d30 .functor XOR 1, L_0x55ec338243b0, L_0x55ec33823b30, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381d130_0 .net "A", 0 0, L_0x55ec338243b0; alias, 1 drivers
|
||||||
|
v0x55ec3381d210_0 .net "B", 0 0, L_0x55ec33823b30; alias, 1 drivers
|
||||||
|
v0x55ec3381d2d0_0 .net "Carry", 0 0, L_0x55ec33823ba0; alias, 1 drivers
|
||||||
|
v0x55ec3381d3a0_0 .net "Sum", 0 0, L_0x55ec33823d30; alias, 1 drivers
|
||||||
|
S_0x55ec3381d510 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381cc60;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x55ec33823dc0 .functor AND 1, L_0x55ec33823d30, L_0x55ec33824660, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33823f00 .functor XOR 1, L_0x55ec33823d30, L_0x55ec33824660, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381d780_0 .net "A", 0 0, L_0x55ec33823d30; alias, 1 drivers
|
||||||
|
v0x55ec3381d850_0 .net "B", 0 0, L_0x55ec33824660; alias, 1 drivers
|
||||||
|
v0x55ec3381d8f0_0 .net "Carry", 0 0, L_0x55ec33823dc0; alias, 1 drivers
|
||||||
|
v0x55ec3381d9c0_0 .net "Sum", 0 0, L_0x55ec33823f00; alias, 1 drivers
|
||||||
|
S_0x55ec3381e1e0 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381c9e0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A0";
|
||||||
|
.port_info 1 /INPUT 1 "A1";
|
||||||
|
.port_info 2 /INPUT 1 "S";
|
||||||
|
.port_info 3 /OUTPUT 1 "Y";
|
||||||
|
L_0x55ec33824160 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x55ec338241f0 .functor AND 1, L_0x55ec33823f00, L_0x55ec338223e0, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33824280 .functor AND 1, L_0x55ec33824160, L_0x55ec338243b0, C4<1>, C4<1>;
|
||||||
|
L_0x55ec338242f0 .functor OR 1, L_0x55ec338241f0, L_0x55ec33824280, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381e430_0 .net "A0", 0 0, L_0x55ec338243b0; alias, 1 drivers
|
||||||
|
v0x55ec3381e520_0 .net "A1", 0 0, L_0x55ec33823f00; alias, 1 drivers
|
||||||
|
v0x55ec3381e630_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||||
|
v0x55ec3381e6d0_0 .net "Y", 0 0, L_0x55ec338242f0; alias, 1 drivers
|
||||||
|
v0x55ec3381e770_0 .net "and1", 0 0, L_0x55ec338241f0; 1 drivers
|
||||||
|
v0x55ec3381e880_0 .net "and2", 0 0, L_0x55ec33824280; 1 drivers
|
||||||
|
v0x55ec3381e940_0 .net "notS", 0 0, L_0x55ec33824160; 1 drivers
|
||||||
|
S_0x55ec3381f0f0 .scope module, "PU4" "PU" 3 45, 4 1 0, S_0x55ec337fa3a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Cin";
|
||||||
|
.port_info 3 /INPUT 1 "S";
|
||||||
|
.port_info 4 /OUTPUT 1 "Y";
|
||||||
|
.port_info 5 /OUTPUT 1 "COut";
|
||||||
|
L_0x55ec338247f0 .functor NOT 1, L_0x55ec33825100, C4<0>, C4<0>, C4<0>;
|
||||||
|
v0x55ec33821210_0 .net "A", 0 0, L_0x55ec33825060; 1 drivers
|
||||||
|
v0x55ec338212d0_0 .net "B", 0 0, L_0x55ec33825100; 1 drivers
|
||||||
|
v0x55ec33821390_0 .net "COut", 0 0, L_0x55ec33824db0; 1 drivers
|
||||||
|
v0x55ec33821430_0 .net "Cin", 0 0, L_0x55ec33825210; 1 drivers
|
||||||
|
v0x55ec33821520_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||||
|
v0x55ec33821610_0 .net "Sum", 0 0, L_0x55ec33824c00; 1 drivers
|
||||||
|
v0x55ec338216b0_0 .net "Y", 0 0, L_0x55ec33824ff0; 1 drivers
|
||||||
|
v0x55ec33821750_0 .net "notB", 0 0, L_0x55ec338247f0; 1 drivers
|
||||||
|
S_0x55ec3381f370 .scope module, "f1" "fulladder" 4 16, 5 1 0, S_0x55ec3381f0f0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /INPUT 1 "Carry";
|
||||||
|
.port_info 3 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 4 /OUTPUT 1 "CarryO";
|
||||||
|
L_0x55ec33824db0 .functor OR 1, L_0x55ec33824860, L_0x55ec33824ac0, C4<0>, C4<0>;
|
||||||
|
v0x55ec33820290_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
|
||||||
|
v0x55ec33820350_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
|
||||||
|
v0x55ec33820420_0 .net "Carry", 0 0, L_0x55ec33825210; alias, 1 drivers
|
||||||
|
v0x55ec33820520_0 .net "CarryO", 0 0, L_0x55ec33824db0; alias, 1 drivers
|
||||||
|
v0x55ec338205c0_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
|
||||||
|
v0x55ec338206b0_0 .net "and1", 0 0, L_0x55ec33824860; 1 drivers
|
||||||
|
v0x55ec33820780_0 .net "and2", 0 0, L_0x55ec33824ac0; 1 drivers
|
||||||
|
v0x55ec33820850_0 .net "xor1", 0 0, L_0x55ec33824a30; 1 drivers
|
||||||
|
S_0x55ec3381f5f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55ec3381f370;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x55ec33824860 .functor AND 1, L_0x55ec33825060, L_0x55ec338247f0, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33824a30 .functor XOR 1, L_0x55ec33825060, L_0x55ec338247f0, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381f890_0 .net "A", 0 0, L_0x55ec33825060; alias, 1 drivers
|
||||||
|
v0x55ec3381f970_0 .net "B", 0 0, L_0x55ec338247f0; alias, 1 drivers
|
||||||
|
v0x55ec3381fa30_0 .net "Carry", 0 0, L_0x55ec33824860; alias, 1 drivers
|
||||||
|
v0x55ec3381fb00_0 .net "Sum", 0 0, L_0x55ec33824a30; alias, 1 drivers
|
||||||
|
S_0x55ec3381fc70 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55ec3381f370;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A";
|
||||||
|
.port_info 1 /INPUT 1 "B";
|
||||||
|
.port_info 2 /OUTPUT 1 "Sum";
|
||||||
|
.port_info 3 /OUTPUT 1 "Carry";
|
||||||
|
L_0x55ec33824ac0 .functor AND 1, L_0x55ec33824a30, L_0x55ec33825210, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33824c00 .functor XOR 1, L_0x55ec33824a30, L_0x55ec33825210, C4<0>, C4<0>;
|
||||||
|
v0x55ec3381fee0_0 .net "A", 0 0, L_0x55ec33824a30; alias, 1 drivers
|
||||||
|
v0x55ec3381ffb0_0 .net "B", 0 0, L_0x55ec33825210; alias, 1 drivers
|
||||||
|
v0x55ec33820050_0 .net "Carry", 0 0, L_0x55ec33824ac0; alias, 1 drivers
|
||||||
|
v0x55ec33820120_0 .net "Sum", 0 0, L_0x55ec33824c00; alias, 1 drivers
|
||||||
|
S_0x55ec33820940 .scope module, "m1" "mux2" 4 25, 7 1 0, S_0x55ec3381f0f0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 1 "A0";
|
||||||
|
.port_info 1 /INPUT 1 "A1";
|
||||||
|
.port_info 2 /INPUT 1 "S";
|
||||||
|
.port_info 3 /OUTPUT 1 "Y";
|
||||||
|
L_0x55ec33824e60 .functor NOT 1, L_0x55ec338223e0, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x55ec33824ef0 .functor AND 1, L_0x55ec33824c00, L_0x55ec338223e0, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33824f80 .functor AND 1, L_0x55ec33824e60, L_0x55ec33825060, C4<1>, C4<1>;
|
||||||
|
L_0x55ec33824ff0 .functor OR 1, L_0x55ec33824ef0, L_0x55ec33824f80, C4<0>, C4<0>;
|
||||||
|
v0x55ec33820b90_0 .net "A0", 0 0, L_0x55ec33825060; alias, 1 drivers
|
||||||
|
v0x55ec33820c80_0 .net "A1", 0 0, L_0x55ec33824c00; alias, 1 drivers
|
||||||
|
v0x55ec33820d90_0 .net "S", 0 0, L_0x55ec338223e0; alias, 1 drivers
|
||||||
|
v0x55ec33820e80_0 .net "Y", 0 0, L_0x55ec33824ff0; alias, 1 drivers
|
||||||
|
v0x55ec33820f20_0 .net "and1", 0 0, L_0x55ec33824ef0; 1 drivers
|
||||||
|
v0x55ec33821010_0 .net "and2", 0 0, L_0x55ec33824f80; 1 drivers
|
||||||
|
v0x55ec338210d0_0 .net "notS", 0 0, L_0x55ec33824e60; 1 drivers
|
||||||
|
.scope S_0x55ec337fbbf0;
|
||||||
|
T_0 ;
|
||||||
|
%vpi_call 2 21 "$monitor", "Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b", $time, v0x55ec33821ff0_0, v0x55ec338220d0_0, v0x55ec33822170_0, v0x55ec33822240_0 {0 0 0};
|
||||||
|
%vpi_call 2 23 "$dumpfile", "divider4.vcd" {0 0 0};
|
||||||
|
%vpi_call 2 24 "$dumpvars" {0 0 0};
|
||||||
|
%pushi/vec4 8, 0, 4;
|
||||||
|
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||||
|
%pushi/vec4 2, 0, 2;
|
||||||
|
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||||
|
%delay 10, 0;
|
||||||
|
%pushi/vec4 15, 0, 4;
|
||||||
|
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||||
|
%pushi/vec4 3, 0, 2;
|
||||||
|
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||||
|
%delay 10, 0;
|
||||||
|
%pushi/vec4 7, 0, 4;
|
||||||
|
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||||
|
%pushi/vec4 2, 0, 2;
|
||||||
|
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||||
|
%delay 10, 0;
|
||||||
|
%pushi/vec4 9, 0, 4;
|
||||||
|
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||||
|
%pushi/vec4 3, 0, 2;
|
||||||
|
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||||
|
%delay 10, 0;
|
||||||
|
%pushi/vec4 6, 0, 4;
|
||||||
|
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||||
|
%pushi/vec4 1, 0, 2;
|
||||||
|
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||||
|
%delay 10, 0;
|
||||||
|
%pushi/vec4 10, 0, 4;
|
||||||
|
%store/vec4 v0x55ec33821ff0_0, 0, 4;
|
||||||
|
%pushi/vec4 0, 0, 2;
|
||||||
|
%store/vec4 v0x55ec338220d0_0, 0, 2;
|
||||||
|
%delay 10, 0;
|
||||||
|
%vpi_call 2 57 "$finish" {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_0;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 8;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"divider4TB.v";
|
||||||
|
"divider4.v";
|
||||||
|
"PU.v";
|
||||||
|
"fulladder.v";
|
||||||
|
"halfadder.v";
|
||||||
|
"mux2.v";
|
||||||
58
project0.2/divider4.v
Normal file
58
project0.2/divider4.v
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
module divider4 (
|
||||||
|
input [3:0] Dividend, // 4-bit dividend
|
||||||
|
input [1:0] Divisor, // 2-bit divisor
|
||||||
|
output [3:0] Quotient, // 4-bit quotient
|
||||||
|
output [2:0] Remainder // 3-bit remainder
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [3:0] Carry; // Carry wires between PUs
|
||||||
|
wire [3:0] Y; // Intermediate PU outputs
|
||||||
|
wire S0, S1; // Select signals based on division logic
|
||||||
|
|
||||||
|
// Calculate select signals based on carry outputs
|
||||||
|
assign S0 = Carry[3]; // First select signal
|
||||||
|
assign S1 = Carry[2]; // Second select signal
|
||||||
|
|
||||||
|
// Row 1
|
||||||
|
PU PU1 (
|
||||||
|
.A(Dividend[3]),
|
||||||
|
.B(Divisor[1]),
|
||||||
|
.Cin(1'b0), // Initial carry input is 0
|
||||||
|
.S(S0),
|
||||||
|
.Y(Y[3]),
|
||||||
|
.COut(Carry[3])
|
||||||
|
);
|
||||||
|
|
||||||
|
PU PU2 (
|
||||||
|
.A(Dividend[2]),
|
||||||
|
.B(Divisor[1]),
|
||||||
|
.Cin(Carry[3]),
|
||||||
|
.S(S0),
|
||||||
|
.Y(Y[2]),
|
||||||
|
.COut(Carry[2])
|
||||||
|
);
|
||||||
|
|
||||||
|
// Row 2
|
||||||
|
PU PU3 (
|
||||||
|
.A(Dividend[1]),
|
||||||
|
.B(Divisor[0]),
|
||||||
|
.Cin(Carry[2]),
|
||||||
|
.S(S1),
|
||||||
|
.Y(Y[1]),
|
||||||
|
.COut(Carry[1])
|
||||||
|
);
|
||||||
|
|
||||||
|
PU PU4 (
|
||||||
|
.A(Dividend[0]),
|
||||||
|
.B(Divisor[0]),
|
||||||
|
.Cin(Carry[1]),
|
||||||
|
.S(S1),
|
||||||
|
.Y(Y[0]),
|
||||||
|
.COut(Carry[0])
|
||||||
|
);
|
||||||
|
|
||||||
|
// Assign outputs
|
||||||
|
assign Quotient = Y; // Output of the PUs is the quotient
|
||||||
|
assign Remainder = Carry; // Final carry values are the remainder
|
||||||
|
|
||||||
|
endmodule
|
||||||
457
project0.2/divider4.vcd
Normal file
457
project0.2/divider4.vcd
Normal file
@ -0,0 +1,457 @@
|
|||||||
|
$date
|
||||||
|
Fri Dec 27 21:47:45 2024
|
||||||
|
$end
|
||||||
|
$version
|
||||||
|
Icarus Verilog
|
||||||
|
$end
|
||||||
|
$timescale
|
||||||
|
1s
|
||||||
|
$end
|
||||||
|
$scope module divider4TB $end
|
||||||
|
$var wire 3 ! Remainder [2:0] $end
|
||||||
|
$var wire 4 " Quotient [3:0] $end
|
||||||
|
$var reg 4 # Dividend [3:0] $end
|
||||||
|
$var reg 2 $ Divisor [1:0] $end
|
||||||
|
$scope module uut $end
|
||||||
|
$var wire 4 % Dividend [3:0] $end
|
||||||
|
$var wire 2 & Divisor [1:0] $end
|
||||||
|
$var wire 4 ' Quotient [3:0] $end
|
||||||
|
$var wire 4 ( Y [3:0] $end
|
||||||
|
$var wire 1 ) S1 $end
|
||||||
|
$var wire 1 * S0 $end
|
||||||
|
$var wire 3 + Remainder [2:0] $end
|
||||||
|
$var wire 4 , Carry [3:0] $end
|
||||||
|
$scope module PU1 $end
|
||||||
|
$var wire 1 - A $end
|
||||||
|
$var wire 1 . B $end
|
||||||
|
$var wire 1 / Cin $end
|
||||||
|
$var wire 1 * S $end
|
||||||
|
$var wire 1 0 notB $end
|
||||||
|
$var wire 1 1 Y $end
|
||||||
|
$var wire 1 2 Sum $end
|
||||||
|
$var wire 1 3 COut $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 - A $end
|
||||||
|
$var wire 1 0 B $end
|
||||||
|
$var wire 1 / Carry $end
|
||||||
|
$var wire 1 3 CarryO $end
|
||||||
|
$var wire 1 4 xor1 $end
|
||||||
|
$var wire 1 5 and2 $end
|
||||||
|
$var wire 1 6 and1 $end
|
||||||
|
$var wire 1 2 Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 - A $end
|
||||||
|
$var wire 1 0 B $end
|
||||||
|
$var wire 1 6 Carry $end
|
||||||
|
$var wire 1 4 Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 4 A $end
|
||||||
|
$var wire 1 / B $end
|
||||||
|
$var wire 1 5 Carry $end
|
||||||
|
$var wire 1 2 Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module m1 $end
|
||||||
|
$var wire 1 - A0 $end
|
||||||
|
$var wire 1 2 A1 $end
|
||||||
|
$var wire 1 * S $end
|
||||||
|
$var wire 1 1 Y $end
|
||||||
|
$var wire 1 7 and1 $end
|
||||||
|
$var wire 1 8 and2 $end
|
||||||
|
$var wire 1 9 notS $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module PU2 $end
|
||||||
|
$var wire 1 : A $end
|
||||||
|
$var wire 1 ; B $end
|
||||||
|
$var wire 1 < Cin $end
|
||||||
|
$var wire 1 * S $end
|
||||||
|
$var wire 1 = notB $end
|
||||||
|
$var wire 1 > Y $end
|
||||||
|
$var wire 1 ? Sum $end
|
||||||
|
$var wire 1 @ COut $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 : A $end
|
||||||
|
$var wire 1 = B $end
|
||||||
|
$var wire 1 < Carry $end
|
||||||
|
$var wire 1 @ CarryO $end
|
||||||
|
$var wire 1 A xor1 $end
|
||||||
|
$var wire 1 B and2 $end
|
||||||
|
$var wire 1 C and1 $end
|
||||||
|
$var wire 1 ? Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 : A $end
|
||||||
|
$var wire 1 = B $end
|
||||||
|
$var wire 1 C Carry $end
|
||||||
|
$var wire 1 A Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 A A $end
|
||||||
|
$var wire 1 < B $end
|
||||||
|
$var wire 1 B Carry $end
|
||||||
|
$var wire 1 ? Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module m1 $end
|
||||||
|
$var wire 1 : A0 $end
|
||||||
|
$var wire 1 ? A1 $end
|
||||||
|
$var wire 1 * S $end
|
||||||
|
$var wire 1 > Y $end
|
||||||
|
$var wire 1 D and1 $end
|
||||||
|
$var wire 1 E and2 $end
|
||||||
|
$var wire 1 F notS $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module PU3 $end
|
||||||
|
$var wire 1 G A $end
|
||||||
|
$var wire 1 H B $end
|
||||||
|
$var wire 1 I Cin $end
|
||||||
|
$var wire 1 ) S $end
|
||||||
|
$var wire 1 J notB $end
|
||||||
|
$var wire 1 K Y $end
|
||||||
|
$var wire 1 L Sum $end
|
||||||
|
$var wire 1 M COut $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 G A $end
|
||||||
|
$var wire 1 J B $end
|
||||||
|
$var wire 1 I Carry $end
|
||||||
|
$var wire 1 M CarryO $end
|
||||||
|
$var wire 1 N xor1 $end
|
||||||
|
$var wire 1 O and2 $end
|
||||||
|
$var wire 1 P and1 $end
|
||||||
|
$var wire 1 L Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 G A $end
|
||||||
|
$var wire 1 J B $end
|
||||||
|
$var wire 1 P Carry $end
|
||||||
|
$var wire 1 N Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 N A $end
|
||||||
|
$var wire 1 I B $end
|
||||||
|
$var wire 1 O Carry $end
|
||||||
|
$var wire 1 L Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module m1 $end
|
||||||
|
$var wire 1 G A0 $end
|
||||||
|
$var wire 1 L A1 $end
|
||||||
|
$var wire 1 ) S $end
|
||||||
|
$var wire 1 K Y $end
|
||||||
|
$var wire 1 Q and1 $end
|
||||||
|
$var wire 1 R and2 $end
|
||||||
|
$var wire 1 S notS $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module PU4 $end
|
||||||
|
$var wire 1 T A $end
|
||||||
|
$var wire 1 U B $end
|
||||||
|
$var wire 1 V Cin $end
|
||||||
|
$var wire 1 ) S $end
|
||||||
|
$var wire 1 W notB $end
|
||||||
|
$var wire 1 X Y $end
|
||||||
|
$var wire 1 Y Sum $end
|
||||||
|
$var wire 1 Z COut $end
|
||||||
|
$scope module f1 $end
|
||||||
|
$var wire 1 T A $end
|
||||||
|
$var wire 1 W B $end
|
||||||
|
$var wire 1 V Carry $end
|
||||||
|
$var wire 1 Z CarryO $end
|
||||||
|
$var wire 1 [ xor1 $end
|
||||||
|
$var wire 1 \ and2 $end
|
||||||
|
$var wire 1 ] and1 $end
|
||||||
|
$var wire 1 Y Sum $end
|
||||||
|
$scope module h1 $end
|
||||||
|
$var wire 1 T A $end
|
||||||
|
$var wire 1 W B $end
|
||||||
|
$var wire 1 ] Carry $end
|
||||||
|
$var wire 1 [ Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module h2 $end
|
||||||
|
$var wire 1 [ A $end
|
||||||
|
$var wire 1 V B $end
|
||||||
|
$var wire 1 \ Carry $end
|
||||||
|
$var wire 1 Y Sum $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$scope module m1 $end
|
||||||
|
$var wire 1 T A0 $end
|
||||||
|
$var wire 1 Y A1 $end
|
||||||
|
$var wire 1 ) S $end
|
||||||
|
$var wire 1 X Y $end
|
||||||
|
$var wire 1 ^ and1 $end
|
||||||
|
$var wire 1 _ and2 $end
|
||||||
|
$var wire 1 ` notS $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$enddefinitions $end
|
||||||
|
#0
|
||||||
|
$dumpvars
|
||||||
|
1`
|
||||||
|
0_
|
||||||
|
0^
|
||||||
|
0]
|
||||||
|
0\
|
||||||
|
1[
|
||||||
|
0Z
|
||||||
|
1Y
|
||||||
|
0X
|
||||||
|
1W
|
||||||
|
0V
|
||||||
|
0U
|
||||||
|
0T
|
||||||
|
1S
|
||||||
|
0R
|
||||||
|
0Q
|
||||||
|
0P
|
||||||
|
0O
|
||||||
|
1N
|
||||||
|
0M
|
||||||
|
1L
|
||||||
|
0K
|
||||||
|
1J
|
||||||
|
0I
|
||||||
|
0H
|
||||||
|
0G
|
||||||
|
1F
|
||||||
|
0E
|
||||||
|
0D
|
||||||
|
0C
|
||||||
|
0B
|
||||||
|
0A
|
||||||
|
0@
|
||||||
|
0?
|
||||||
|
0>
|
||||||
|
0=
|
||||||
|
0<
|
||||||
|
1;
|
||||||
|
0:
|
||||||
|
19
|
||||||
|
18
|
||||||
|
07
|
||||||
|
06
|
||||||
|
05
|
||||||
|
14
|
||||||
|
03
|
||||||
|
12
|
||||||
|
11
|
||||||
|
00
|
||||||
|
0/
|
||||||
|
1.
|
||||||
|
1-
|
||||||
|
b0 ,
|
||||||
|
b0 +
|
||||||
|
0*
|
||||||
|
0)
|
||||||
|
b1000 (
|
||||||
|
b1000 '
|
||||||
|
b10 &
|
||||||
|
b1000 %
|
||||||
|
b10 $
|
||||||
|
b1000 #
|
||||||
|
b1000 "
|
||||||
|
b0 !
|
||||||
|
$end
|
||||||
|
#10
|
||||||
|
0\
|
||||||
|
0V
|
||||||
|
b0 !
|
||||||
|
b0 +
|
||||||
|
1?
|
||||||
|
1>
|
||||||
|
0M
|
||||||
|
1L
|
||||||
|
1K
|
||||||
|
b0 ,
|
||||||
|
0Z
|
||||||
|
1Y
|
||||||
|
b1111 "
|
||||||
|
b1111 '
|
||||||
|
b1111 (
|
||||||
|
1X
|
||||||
|
0J
|
||||||
|
0W
|
||||||
|
1A
|
||||||
|
1E
|
||||||
|
0P
|
||||||
|
1N
|
||||||
|
1R
|
||||||
|
0]
|
||||||
|
1[
|
||||||
|
1_
|
||||||
|
1H
|
||||||
|
1U
|
||||||
|
1:
|
||||||
|
1G
|
||||||
|
1T
|
||||||
|
b11 $
|
||||||
|
b11 &
|
||||||
|
b1111 #
|
||||||
|
b1111 %
|
||||||
|
#20
|
||||||
|
1V
|
||||||
|
b11 !
|
||||||
|
b11 +
|
||||||
|
1M
|
||||||
|
0L
|
||||||
|
b11 ,
|
||||||
|
1Z
|
||||||
|
1Y
|
||||||
|
1P
|
||||||
|
0N
|
||||||
|
1]
|
||||||
|
0[
|
||||||
|
02
|
||||||
|
b111 "
|
||||||
|
b111 '
|
||||||
|
b111 (
|
||||||
|
01
|
||||||
|
1J
|
||||||
|
1W
|
||||||
|
04
|
||||||
|
08
|
||||||
|
0H
|
||||||
|
0U
|
||||||
|
0-
|
||||||
|
b10 $
|
||||||
|
b10 &
|
||||||
|
b111 #
|
||||||
|
b111 %
|
||||||
|
#30
|
||||||
|
0Z
|
||||||
|
b0 !
|
||||||
|
b0 +
|
||||||
|
0V
|
||||||
|
0]
|
||||||
|
1[
|
||||||
|
12
|
||||||
|
11
|
||||||
|
0?
|
||||||
|
0>
|
||||||
|
b0 ,
|
||||||
|
0M
|
||||||
|
0L
|
||||||
|
b1001 "
|
||||||
|
b1001 '
|
||||||
|
b1001 (
|
||||||
|
0K
|
||||||
|
0J
|
||||||
|
0W
|
||||||
|
14
|
||||||
|
18
|
||||||
|
0A
|
||||||
|
0E
|
||||||
|
0P
|
||||||
|
0N
|
||||||
|
0R
|
||||||
|
1H
|
||||||
|
1U
|
||||||
|
1-
|
||||||
|
0:
|
||||||
|
0G
|
||||||
|
b11 $
|
||||||
|
b11 &
|
||||||
|
b1001 #
|
||||||
|
b1001 %
|
||||||
|
#40
|
||||||
|
1^
|
||||||
|
1V
|
||||||
|
1M
|
||||||
|
1O
|
||||||
|
0S
|
||||||
|
0Q
|
||||||
|
0`
|
||||||
|
b110 !
|
||||||
|
b110 +
|
||||||
|
1I
|
||||||
|
1)
|
||||||
|
b110 ,
|
||||||
|
1@
|
||||||
|
1C
|
||||||
|
12
|
||||||
|
01
|
||||||
|
0?
|
||||||
|
1>
|
||||||
|
0L
|
||||||
|
0K
|
||||||
|
1Y
|
||||||
|
b101 "
|
||||||
|
b101 '
|
||||||
|
b101 (
|
||||||
|
1X
|
||||||
|
10
|
||||||
|
1=
|
||||||
|
14
|
||||||
|
08
|
||||||
|
0A
|
||||||
|
1E
|
||||||
|
1N
|
||||||
|
0R
|
||||||
|
0[
|
||||||
|
0_
|
||||||
|
0.
|
||||||
|
0;
|
||||||
|
0-
|
||||||
|
1:
|
||||||
|
1G
|
||||||
|
0T
|
||||||
|
b1 $
|
||||||
|
b1 &
|
||||||
|
b110 #
|
||||||
|
b110 %
|
||||||
|
#50
|
||||||
|
1Q
|
||||||
|
1L
|
||||||
|
1K
|
||||||
|
0R
|
||||||
|
0X
|
||||||
|
1Z
|
||||||
|
1B
|
||||||
|
09
|
||||||
|
0F
|
||||||
|
0D
|
||||||
|
0S
|
||||||
|
0`
|
||||||
|
0^
|
||||||
|
0O
|
||||||
|
1\
|
||||||
|
0Y
|
||||||
|
1<
|
||||||
|
1*
|
||||||
|
b111 !
|
||||||
|
b111 +
|
||||||
|
1I
|
||||||
|
1)
|
||||||
|
1P
|
||||||
|
0N
|
||||||
|
1[
|
||||||
|
13
|
||||||
|
02
|
||||||
|
01
|
||||||
|
b1111 ,
|
||||||
|
1@
|
||||||
|
0?
|
||||||
|
b10 "
|
||||||
|
b10 '
|
||||||
|
b10 (
|
||||||
|
0>
|
||||||
|
1J
|
||||||
|
1W
|
||||||
|
16
|
||||||
|
04
|
||||||
|
08
|
||||||
|
0C
|
||||||
|
1A
|
||||||
|
0E
|
||||||
|
0H
|
||||||
|
0U
|
||||||
|
1-
|
||||||
|
0:
|
||||||
|
b0 $
|
||||||
|
b0 &
|
||||||
|
b1010 #
|
||||||
|
b1010 %
|
||||||
|
#60
|
||||||
60
project0.2/divider4TB.v
Normal file
60
project0.2/divider4TB.v
Normal file
@ -0,0 +1,60 @@
|
|||||||
|
module divider4TB;
|
||||||
|
|
||||||
|
// Inputs
|
||||||
|
reg [3:0] Dividend;
|
||||||
|
reg [1:0] Divisor;
|
||||||
|
|
||||||
|
// Outputs
|
||||||
|
wire [3:0] Quotient;
|
||||||
|
wire [2:0] Remainder;
|
||||||
|
|
||||||
|
// Instantiate the Unit Under Test (UUT)
|
||||||
|
divider4 uut (
|
||||||
|
.Dividend(Dividend),
|
||||||
|
.Divisor(Divisor),
|
||||||
|
.Quotient(Quotient),
|
||||||
|
.Remainder(Remainder)
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
// Monitor output changes
|
||||||
|
$monitor("Time=%0t | Dividend=%b | Divisor=%b | Quotient=%b | Remainder=%b",
|
||||||
|
$time, Dividend, Divisor, Quotient, Remainder);
|
||||||
|
$dumpfile("divider4.vcd");
|
||||||
|
$dumpvars;
|
||||||
|
|
||||||
|
// Test Case 1: 8 / 2
|
||||||
|
Dividend = 4'b1000; // 8 in binary
|
||||||
|
Divisor = 2'b10; // 2 in binary
|
||||||
|
#10;
|
||||||
|
|
||||||
|
// Test Case 2: 15 / 3
|
||||||
|
Dividend = 4'b1111; // 15 in binary
|
||||||
|
Divisor = 2'b11; // 3 in binary
|
||||||
|
#10;
|
||||||
|
|
||||||
|
// Test Case 3: 7 / 2
|
||||||
|
Dividend = 4'b0111; // 7 in binary
|
||||||
|
Divisor = 2'b10; // 2 in binary
|
||||||
|
#10;
|
||||||
|
|
||||||
|
// Test Case 4: 9 / 3
|
||||||
|
Dividend = 4'b1001; // 9 in binary
|
||||||
|
Divisor = 2'b11; // 3 in binary
|
||||||
|
#10;
|
||||||
|
|
||||||
|
// Test Case 5: 6 / 1
|
||||||
|
Dividend = 4'b0110; // 6 in binary
|
||||||
|
Divisor = 2'b01; // 1 in binary
|
||||||
|
#10;
|
||||||
|
|
||||||
|
// Test Case 6: Division by 0 (should be undefined behavior)
|
||||||
|
Dividend = 4'b1010; // 10 in binary
|
||||||
|
Divisor = 2'b00; // Division by zero
|
||||||
|
#10;
|
||||||
|
|
||||||
|
// End simulation
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
16
project0.2/mux2.v
Normal file
16
project0.2/mux2.v
Normal file
@ -0,0 +1,16 @@
|
|||||||
|
module mux2 (
|
||||||
|
input A0, A1,
|
||||||
|
input S,
|
||||||
|
output Y
|
||||||
|
);
|
||||||
|
|
||||||
|
wire notS, and1, and2;
|
||||||
|
|
||||||
|
not n1 (notS, S);
|
||||||
|
|
||||||
|
and an1 (and1, A1, S);
|
||||||
|
and an2 (and2, notS, A0);
|
||||||
|
|
||||||
|
or o1 (Y, and1, and2);
|
||||||
|
|
||||||
|
endmodule
|
||||||
318
project0.2/selector
Normal file
318
project0.2/selector
Normal file
@ -0,0 +1,318 @@
|
|||||||
|
#! /usr/bin/vvp
|
||||||
|
:ivl_version "11.0 (stable)";
|
||||||
|
:ivl_delay_selection "TYPICAL";
|
||||||
|
:vpi_time_precision + 0;
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||||
|
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||||
|
S_0x564261ee80a0 .scope module, "selectorTB" "selectorTB" 2 1;
|
||||||
|
.timescale 0 0;
|
||||||
|
v0x564261f0f000_0 .var "A", 3 0;
|
||||||
|
v0x564261f0f0e0_0 .var "B", 3 0;
|
||||||
|
v0x564261f0f1b0_0 .var "Y", 7 0;
|
||||||
|
v0x564261f0f280_0 .var "opCodeA", 2 0;
|
||||||
|
v0x564261f0f370_0 .net "s0", 7 0, L_0x564261f18a20; 1 drivers
|
||||||
|
v0x564261f0f410_0 .var "select", 3 0;
|
||||||
|
S_0x564261eda760 .scope module, "uut" "selector" 2 8, 3 1 0, S_0x564261ee80a0;
|
||||||
|
.timescale 0 0;
|
||||||
|
.port_info 0 /INPUT 4 "select";
|
||||||
|
.port_info 1 /INPUT 8 "Y";
|
||||||
|
.port_info 2 /INPUT 4 "A";
|
||||||
|
.port_info 3 /INPUT 4 "B";
|
||||||
|
.port_info 4 /INPUT 3 "opCodeA";
|
||||||
|
.port_info 5 /OUTPUT 8 "s0";
|
||||||
|
L_0x564261f0f4e0 .functor AND 1, L_0x564261f0f5e0, L_0x564261f0f720, C4<1>, C4<1>;
|
||||||
|
L_0x564261f0f860 .functor AND 1, L_0x564261f0f8d0, L_0x564261f0f9c0, C4<1>, C4<1>;
|
||||||
|
L_0x564261f0fae0 .functor AND 1, L_0x564261f0fb50, L_0x564261f0fc40, C4<1>, C4<1>;
|
||||||
|
L_0x564261f0fe60 .functor AND 1, L_0x564261f0ff50, L_0x564261f10090, C4<1>, C4<1>;
|
||||||
|
L_0x564261f10180 .functor AND 1, L_0x564261f101f0, L_0x564261f10340, C4<1>, C4<1>;
|
||||||
|
L_0x564261f10430 .functor AND 1, L_0x564261f104e0, L_0x564261f10640, C4<1>, C4<1>;
|
||||||
|
L_0x564261f10730 .functor AND 1, L_0x564261f107a0, L_0x564261f10910, C4<1>, C4<1>;
|
||||||
|
L_0x564261f105d0 .functor AND 1, L_0x564261f10c70, L_0x564261f10d60, C4<1>, C4<1>;
|
||||||
|
L_0x564261f10ef0 .functor AND 1, L_0x564261f10f60, L_0x564261f11050, C4<1>, C4<1>;
|
||||||
|
L_0x564261f111f0 .functor AND 1, L_0x564261f10e50, L_0x564261f112f0, C4<1>, C4<1>;
|
||||||
|
L_0x564261f114f0 .functor AND 1, L_0x564261f11560, L_0x564261f11650, C4<1>, C4<1>;
|
||||||
|
L_0x564261f11810 .functor AND 1, L_0x564261f11920, L_0x564261f11a10, C4<1>, C4<1>;
|
||||||
|
L_0x564261f11be0 .functor AND 1, L_0x564261f11c80, L_0x564261f11d20, C4<1>, C4<1>;
|
||||||
|
L_0x564261f11f00 .functor AND 1, L_0x564261f12020, L_0x564261f12110, C4<1>, C4<1>;
|
||||||
|
L_0x564261f118b0 .functor AND 1, L_0x564261f12330, L_0x564261f12420, C4<1>, C4<1>;
|
||||||
|
L_0x564261f12940 .functor AND 1, L_0x564261f12a90, L_0x564261f12ca0, C4<1>, C4<1>;
|
||||||
|
L_0x564261f12d90 .functor AND 1, L_0x564261f12e00, L_0x564261f13020, C4<1>, C4<1>;
|
||||||
|
L_0x564261f13160 .functor AND 1, L_0x564261f13270, L_0x564261f134a0, C4<1>, C4<1>;
|
||||||
|
L_0x564261f13820 .functor AND 1, L_0x564261f138e0, L_0x564261f139d0, C4<1>, C4<1>;
|
||||||
|
L_0x564261f13c20 .functor OR 1, L_0x564261f131d0, L_0x564261f13d90, C4<0>, C4<0>;
|
||||||
|
L_0x564261f14040 .functor OR 1, L_0x564261f140b0, L_0x564261f141a0, C4<0>, C4<0>;
|
||||||
|
L_0x564261f14410 .functor OR 1, L_0x564261f14540, L_0x564261f14630, C4<0>, C4<0>;
|
||||||
|
L_0x564261f14a30 .functor OR 1, L_0x564261f14af0, L_0x564261f14d80, C4<0>, C4<0>;
|
||||||
|
L_0x564261f14e70 .functor OR 1, L_0x564261f14fb0, L_0x564261f152a0, C4<0>, C4<0>;
|
||||||
|
L_0x564261f153e0 .functor OR 1, L_0x564261f15450, L_0x564261f15700, C4<0>, C4<0>;
|
||||||
|
L_0x564261f157f0 .functor OR 1, L_0x564261f15940, L_0x564261f15c90, C4<0>, C4<0>;
|
||||||
|
L_0x7f87ae4bf018 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||||
|
L_0x564261f160e0 .functor OR 1, L_0x564261f161a0, L_0x7f87ae4bf018, C4<0>, C4<0>;
|
||||||
|
L_0x564261f162e0 .functor NOR 1, L_0x564261f16440, L_0x564261f16720, C4<0>, C4<0>;
|
||||||
|
L_0x564261f16810 .functor NOR 1, L_0x564261f162e0, L_0x564261f168d0, C4<0>, C4<0>;
|
||||||
|
L_0x564261f16bc0 .functor OR 1, L_0x564261f16d30, L_0x564261f16e70, C4<0>, C4<0>;
|
||||||
|
L_0x564261f171c0 .functor OR 1, L_0x564261f17230, L_0x564261f17320, C4<0>, C4<0>;
|
||||||
|
L_0x564261f17630 .functor OR 1, L_0x564261f177b0, L_0x564261f17930, C4<0>, C4<0>;
|
||||||
|
L_0x564261f17c90 .functor OR 1, L_0x564261f17d00, L_0x564261f17da0, C4<0>, C4<0>;
|
||||||
|
L_0x564261f180d0 .functor AND 1, L_0x564261f182b0, L_0x564261f16810, C4<1>, C4<1>;
|
||||||
|
L_0x564261f183a0 .functor AND 1, L_0x564261f18410, L_0x564261f16810, C4<1>, C4<1>;
|
||||||
|
L_0x564261f18750 .functor AND 1, L_0x564261f18980, L_0x564261f16810, C4<1>, C4<1>;
|
||||||
|
L_0x564261f18ff0 .functor AND 1, L_0x564261f190b0, L_0x564261f16810, C4<1>, C4<1>;
|
||||||
|
v0x564261ee4830_0 .net "A", 3 0, v0x564261f0f000_0; 1 drivers
|
||||||
|
v0x564261ee3bc0_0 .net "B", 3 0, v0x564261f0f0e0_0; 1 drivers
|
||||||
|
o0x7f87ae508078 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
|
||||||
|
v0x564261ee2f20_0 .net "Y", 7 0, o0x7f87ae508078; 0 drivers
|
||||||
|
v0x564261f08470_0 .net *"_ivl_0", 0 0, L_0x564261f0f4e0; 1 drivers
|
||||||
|
v0x564261f08550_0 .net *"_ivl_102", 0 0, L_0x564261f12e00; 1 drivers
|
||||||
|
v0x564261f08680_0 .net *"_ivl_104", 0 0, L_0x564261f13020; 1 drivers
|
||||||
|
v0x564261f08760_0 .net *"_ivl_105", 0 0, L_0x564261f13160; 1 drivers
|
||||||
|
v0x564261f08840_0 .net *"_ivl_108", 0 0, L_0x564261f13270; 1 drivers
|
||||||
|
v0x564261f08920_0 .net *"_ivl_11", 0 0, L_0x564261f0f9c0; 1 drivers
|
||||||
|
v0x564261f08a00_0 .net *"_ivl_110", 0 0, L_0x564261f134a0; 1 drivers
|
||||||
|
v0x564261f08ae0_0 .net *"_ivl_111", 0 0, L_0x564261f13820; 1 drivers
|
||||||
|
v0x564261f08bc0_0 .net *"_ivl_115", 0 0, L_0x564261f138e0; 1 drivers
|
||||||
|
v0x564261f08ca0_0 .net *"_ivl_117", 0 0, L_0x564261f139d0; 1 drivers
|
||||||
|
v0x564261f08d80_0 .net *"_ivl_118", 0 0, L_0x564261f13c20; 1 drivers
|
||||||
|
v0x564261f08e60_0 .net *"_ivl_12", 0 0, L_0x564261f0fae0; 1 drivers
|
||||||
|
v0x564261f08f40_0 .net *"_ivl_121", 0 0, L_0x564261f131d0; 1 drivers
|
||||||
|
v0x564261f09020_0 .net *"_ivl_123", 0 0, L_0x564261f13d90; 1 drivers
|
||||||
|
v0x564261f09100_0 .net *"_ivl_124", 0 0, L_0x564261f14040; 1 drivers
|
||||||
|
v0x564261f091e0_0 .net *"_ivl_127", 0 0, L_0x564261f140b0; 1 drivers
|
||||||
|
v0x564261f092c0_0 .net *"_ivl_129", 0 0, L_0x564261f141a0; 1 drivers
|
||||||
|
v0x564261f093a0_0 .net *"_ivl_130", 0 0, L_0x564261f14410; 1 drivers
|
||||||
|
v0x564261f09480_0 .net *"_ivl_133", 0 0, L_0x564261f14540; 1 drivers
|
||||||
|
v0x564261f09560_0 .net *"_ivl_135", 0 0, L_0x564261f14630; 1 drivers
|
||||||
|
v0x564261f09640_0 .net *"_ivl_136", 0 0, L_0x564261f14a30; 1 drivers
|
||||||
|
v0x564261f09720_0 .net *"_ivl_140", 0 0, L_0x564261f14af0; 1 drivers
|
||||||
|
v0x564261f09800_0 .net *"_ivl_142", 0 0, L_0x564261f14d80; 1 drivers
|
||||||
|
v0x564261f098e0_0 .net *"_ivl_143", 0 0, L_0x564261f14e70; 1 drivers
|
||||||
|
v0x564261f099c0_0 .net *"_ivl_146", 0 0, L_0x564261f14fb0; 1 drivers
|
||||||
|
v0x564261f09aa0_0 .net *"_ivl_148", 0 0, L_0x564261f152a0; 1 drivers
|
||||||
|
v0x564261f09b80_0 .net *"_ivl_149", 0 0, L_0x564261f153e0; 1 drivers
|
||||||
|
v0x564261f09c60_0 .net *"_ivl_15", 0 0, L_0x564261f0fb50; 1 drivers
|
||||||
|
v0x564261f09d40_0 .net *"_ivl_152", 0 0, L_0x564261f15450; 1 drivers
|
||||||
|
v0x564261f09e20_0 .net *"_ivl_154", 0 0, L_0x564261f15700; 1 drivers
|
||||||
|
v0x564261f0a110_0 .net *"_ivl_155", 0 0, L_0x564261f157f0; 1 drivers
|
||||||
|
v0x564261f0a1f0_0 .net *"_ivl_158", 0 0, L_0x564261f15940; 1 drivers
|
||||||
|
v0x564261f0a2d0_0 .net *"_ivl_160", 0 0, L_0x564261f15c90; 1 drivers
|
||||||
|
v0x564261f0a3b0_0 .net *"_ivl_161", 0 0, L_0x564261f160e0; 1 drivers
|
||||||
|
v0x564261f0a490_0 .net *"_ivl_165", 0 0, L_0x564261f161a0; 1 drivers
|
||||||
|
v0x564261f0a570_0 .net/2u *"_ivl_166", 0 0, L_0x7f87ae4bf018; 1 drivers
|
||||||
|
v0x564261f0a650_0 .net *"_ivl_169", 0 0, L_0x564261f16440; 1 drivers
|
||||||
|
v0x564261f0a730_0 .net *"_ivl_17", 0 0, L_0x564261f0fc40; 1 drivers
|
||||||
|
v0x564261f0a810_0 .net *"_ivl_171", 0 0, L_0x564261f16720; 1 drivers
|
||||||
|
v0x564261f0a8f0_0 .net *"_ivl_173", 0 0, L_0x564261f168d0; 1 drivers
|
||||||
|
v0x564261f0a9d0_0 .net *"_ivl_174", 0 0, L_0x564261f16bc0; 1 drivers
|
||||||
|
v0x564261f0aab0_0 .net *"_ivl_177", 0 0, L_0x564261f16d30; 1 drivers
|
||||||
|
v0x564261f0ab90_0 .net *"_ivl_179", 0 0, L_0x564261f16e70; 1 drivers
|
||||||
|
v0x564261f0ac70_0 .net *"_ivl_18", 0 0, L_0x564261f0fe60; 1 drivers
|
||||||
|
v0x564261f0ad50_0 .net *"_ivl_180", 0 0, L_0x564261f171c0; 1 drivers
|
||||||
|
v0x564261f0ae30_0 .net *"_ivl_183", 0 0, L_0x564261f17230; 1 drivers
|
||||||
|
v0x564261f0af10_0 .net *"_ivl_185", 0 0, L_0x564261f17320; 1 drivers
|
||||||
|
v0x564261f0aff0_0 .net *"_ivl_186", 0 0, L_0x564261f17630; 1 drivers
|
||||||
|
v0x564261f0b0d0_0 .net *"_ivl_189", 0 0, L_0x564261f177b0; 1 drivers
|
||||||
|
v0x564261f0b1b0_0 .net *"_ivl_191", 0 0, L_0x564261f17930; 1 drivers
|
||||||
|
v0x564261f0b290_0 .net *"_ivl_192", 0 0, L_0x564261f17c90; 1 drivers
|
||||||
|
v0x564261f0b370_0 .net *"_ivl_195", 0 0, L_0x564261f17d00; 1 drivers
|
||||||
|
v0x564261f0b450_0 .net *"_ivl_197", 0 0, L_0x564261f17da0; 1 drivers
|
||||||
|
v0x564261f0b530_0 .net *"_ivl_198", 0 0, L_0x564261f180d0; 1 drivers
|
||||||
|
v0x564261f0b610_0 .net *"_ivl_201", 0 0, L_0x564261f182b0; 1 drivers
|
||||||
|
v0x564261f0b6f0_0 .net *"_ivl_202", 0 0, L_0x564261f183a0; 1 drivers
|
||||||
|
v0x564261f0b7d0_0 .net *"_ivl_205", 0 0, L_0x564261f18410; 1 drivers
|
||||||
|
v0x564261f0b8b0_0 .net *"_ivl_206", 0 0, L_0x564261f18750; 1 drivers
|
||||||
|
v0x564261f0b990_0 .net *"_ivl_209", 0 0, L_0x564261f18980; 1 drivers
|
||||||
|
v0x564261f0ba70_0 .net *"_ivl_210", 0 0, L_0x564261f18ff0; 1 drivers
|
||||||
|
v0x564261f0bb50_0 .net *"_ivl_214", 0 0, L_0x564261f190b0; 1 drivers
|
||||||
|
v0x564261f0bc30_0 .net *"_ivl_22", 0 0, L_0x564261f0ff50; 1 drivers
|
||||||
|
v0x564261f0c120_0 .net *"_ivl_24", 0 0, L_0x564261f10090; 1 drivers
|
||||||
|
v0x564261f0c200_0 .net *"_ivl_25", 0 0, L_0x564261f10180; 1 drivers
|
||||||
|
v0x564261f0c2e0_0 .net *"_ivl_28", 0 0, L_0x564261f101f0; 1 drivers
|
||||||
|
v0x564261f0c3c0_0 .net *"_ivl_3", 0 0, L_0x564261f0f5e0; 1 drivers
|
||||||
|
v0x564261f0c4a0_0 .net *"_ivl_30", 0 0, L_0x564261f10340; 1 drivers
|
||||||
|
v0x564261f0c580_0 .net *"_ivl_31", 0 0, L_0x564261f10430; 1 drivers
|
||||||
|
v0x564261f0c660_0 .net *"_ivl_34", 0 0, L_0x564261f104e0; 1 drivers
|
||||||
|
v0x564261f0c740_0 .net *"_ivl_36", 0 0, L_0x564261f10640; 1 drivers
|
||||||
|
v0x564261f0c820_0 .net *"_ivl_37", 0 0, L_0x564261f10730; 1 drivers
|
||||||
|
v0x564261f0c900_0 .net *"_ivl_40", 0 0, L_0x564261f107a0; 1 drivers
|
||||||
|
v0x564261f0c9e0_0 .net *"_ivl_42", 0 0, L_0x564261f10910; 1 drivers
|
||||||
|
v0x564261f0cac0_0 .net *"_ivl_43", 0 0, L_0x564261f105d0; 1 drivers
|
||||||
|
v0x564261f0cba0_0 .net *"_ivl_47", 0 0, L_0x564261f10c70; 1 drivers
|
||||||
|
v0x564261f0cc80_0 .net *"_ivl_49", 0 0, L_0x564261f10d60; 1 drivers
|
||||||
|
v0x564261f0cd60_0 .net *"_ivl_5", 0 0, L_0x564261f0f720; 1 drivers
|
||||||
|
v0x564261f0ce40_0 .net *"_ivl_50", 0 0, L_0x564261f10ef0; 1 drivers
|
||||||
|
v0x564261f0cf20_0 .net *"_ivl_53", 0 0, L_0x564261f10f60; 1 drivers
|
||||||
|
v0x564261f0d000_0 .net *"_ivl_55", 0 0, L_0x564261f11050; 1 drivers
|
||||||
|
v0x564261f0d0e0_0 .net *"_ivl_56", 0 0, L_0x564261f111f0; 1 drivers
|
||||||
|
v0x564261f0d1c0_0 .net *"_ivl_59", 0 0, L_0x564261f10e50; 1 drivers
|
||||||
|
v0x564261f0d2a0_0 .net *"_ivl_6", 0 0, L_0x564261f0f860; 1 drivers
|
||||||
|
v0x564261f0d380_0 .net *"_ivl_61", 0 0, L_0x564261f112f0; 1 drivers
|
||||||
|
v0x564261f0d460_0 .net *"_ivl_62", 0 0, L_0x564261f114f0; 1 drivers
|
||||||
|
v0x564261f0d540_0 .net *"_ivl_65", 0 0, L_0x564261f11560; 1 drivers
|
||||||
|
v0x564261f0d620_0 .net *"_ivl_67", 0 0, L_0x564261f11650; 1 drivers
|
||||||
|
v0x564261f0d700_0 .net *"_ivl_68", 0 0, L_0x564261f11810; 1 drivers
|
||||||
|
v0x564261f0d7e0_0 .net *"_ivl_71", 0 0, L_0x564261f11920; 1 drivers
|
||||||
|
v0x564261f0d8c0_0 .net *"_ivl_73", 0 0, L_0x564261f11a10; 1 drivers
|
||||||
|
v0x564261f0d9a0_0 .net *"_ivl_74", 0 0, L_0x564261f11be0; 1 drivers
|
||||||
|
v0x564261f0da80_0 .net *"_ivl_77", 0 0, L_0x564261f11c80; 1 drivers
|
||||||
|
v0x564261f0db60_0 .net *"_ivl_79", 0 0, L_0x564261f11d20; 1 drivers
|
||||||
|
v0x564261f0dc40_0 .net *"_ivl_80", 0 0, L_0x564261f11f00; 1 drivers
|
||||||
|
v0x564261f0dd20_0 .net *"_ivl_83", 0 0, L_0x564261f12020; 1 drivers
|
||||||
|
v0x564261f0de00_0 .net *"_ivl_85", 0 0, L_0x564261f12110; 1 drivers
|
||||||
|
v0x564261f0dee0_0 .net *"_ivl_86", 0 0, L_0x564261f118b0; 1 drivers
|
||||||
|
v0x564261f0dfc0_0 .net *"_ivl_89", 0 0, L_0x564261f12330; 1 drivers
|
||||||
|
v0x564261f0e0a0_0 .net *"_ivl_9", 0 0, L_0x564261f0f8d0; 1 drivers
|
||||||
|
v0x564261f0e180_0 .net *"_ivl_91", 0 0, L_0x564261f12420; 1 drivers
|
||||||
|
v0x564261f0e260_0 .net *"_ivl_92", 0 0, L_0x564261f12940; 1 drivers
|
||||||
|
v0x564261f0e340_0 .net *"_ivl_96", 0 0, L_0x564261f12a90; 1 drivers
|
||||||
|
v0x564261f0e420_0 .net *"_ivl_98", 0 0, L_0x564261f12ca0; 1 drivers
|
||||||
|
v0x564261f0e500_0 .net *"_ivl_99", 0 0, L_0x564261f12d90; 1 drivers
|
||||||
|
v0x564261f0e5e0_0 .net "a0", 3 0, L_0x564261f0fd20; 1 drivers
|
||||||
|
v0x564261f0e6c0_0 .net "b0", 3 0, L_0x564261f10a00; 1 drivers
|
||||||
|
v0x564261f0e7a0_0 .net "op0", 2 0, L_0x564261f13590; 1 drivers
|
||||||
|
v0x564261f0e880_0 .net "opCodeA", 2 0, v0x564261f0f280_0; 1 drivers
|
||||||
|
v0x564261f0e960_0 .net "s0", 7 0, L_0x564261f18a20; alias, 1 drivers
|
||||||
|
v0x564261f0ea40_0 .net "select", 3 0, v0x564261f0f410_0; 1 drivers
|
||||||
|
v0x564261f0eb20_0 .net "tempAB", 3 0, L_0x564261f148f0; 1 drivers
|
||||||
|
v0x564261f0ec00_0 .net "tempYO", 3 0, L_0x564261f15dc0; 1 drivers
|
||||||
|
v0x564261f0ece0_0 .net "temps", 0 0, L_0x564261f16810; 1 drivers
|
||||||
|
v0x564261f0eda0_0 .net "tempsO", 0 0, L_0x564261f162e0; 1 drivers
|
||||||
|
v0x564261f0ee60_0 .net "y0", 7 0, L_0x564261f12620; 1 drivers
|
||||||
|
L_0x564261f0f5e0 .part v0x564261f0f410_0, 0, 1;
|
||||||
|
L_0x564261f0f720 .part v0x564261f0f000_0, 0, 1;
|
||||||
|
L_0x564261f0f8d0 .part v0x564261f0f410_0, 0, 1;
|
||||||
|
L_0x564261f0f9c0 .part v0x564261f0f000_0, 1, 1;
|
||||||
|
L_0x564261f0fb50 .part v0x564261f0f410_0, 0, 1;
|
||||||
|
L_0x564261f0fc40 .part v0x564261f0f000_0, 2, 1;
|
||||||
|
L_0x564261f0fd20 .concat8 [ 1 1 1 1], L_0x564261f0f4e0, L_0x564261f0f860, L_0x564261f0fae0, L_0x564261f0fe60;
|
||||||
|
L_0x564261f0ff50 .part v0x564261f0f410_0, 0, 1;
|
||||||
|
L_0x564261f10090 .part v0x564261f0f000_0, 3, 1;
|
||||||
|
L_0x564261f101f0 .part v0x564261f0f410_0, 1, 1;
|
||||||
|
L_0x564261f10340 .part v0x564261f0f0e0_0, 0, 1;
|
||||||
|
L_0x564261f104e0 .part v0x564261f0f410_0, 1, 1;
|
||||||
|
L_0x564261f10640 .part v0x564261f0f0e0_0, 1, 1;
|
||||||
|
L_0x564261f107a0 .part v0x564261f0f410_0, 1, 1;
|
||||||
|
L_0x564261f10910 .part v0x564261f0f0e0_0, 2, 1;
|
||||||
|
L_0x564261f10a00 .concat8 [ 1 1 1 1], L_0x564261f10180, L_0x564261f10430, L_0x564261f10730, L_0x564261f105d0;
|
||||||
|
L_0x564261f10c70 .part v0x564261f0f410_0, 1, 1;
|
||||||
|
L_0x564261f10d60 .part v0x564261f0f0e0_0, 3, 1;
|
||||||
|
L_0x564261f10f60 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f11050 .part o0x7f87ae508078, 0, 1;
|
||||||
|
L_0x564261f10e50 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f112f0 .part o0x7f87ae508078, 1, 1;
|
||||||
|
L_0x564261f11560 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f11650 .part o0x7f87ae508078, 2, 1;
|
||||||
|
L_0x564261f11920 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f11a10 .part o0x7f87ae508078, 3, 1;
|
||||||
|
L_0x564261f11c80 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f11d20 .part o0x7f87ae508078, 4, 1;
|
||||||
|
L_0x564261f12020 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f12110 .part o0x7f87ae508078, 5, 1;
|
||||||
|
L_0x564261f12330 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f12420 .part o0x7f87ae508078, 6, 1;
|
||||||
|
LS_0x564261f12620_0_0 .concat8 [ 1 1 1 1], L_0x564261f10ef0, L_0x564261f111f0, L_0x564261f114f0, L_0x564261f11810;
|
||||||
|
LS_0x564261f12620_0_4 .concat8 [ 1 1 1 1], L_0x564261f11be0, L_0x564261f11f00, L_0x564261f118b0, L_0x564261f12940;
|
||||||
|
L_0x564261f12620 .concat8 [ 4 4 0 0], LS_0x564261f12620_0_0, LS_0x564261f12620_0_4;
|
||||||
|
L_0x564261f12a90 .part v0x564261f0f410_0, 2, 1;
|
||||||
|
L_0x564261f12ca0 .part o0x7f87ae508078, 7, 1;
|
||||||
|
L_0x564261f12e00 .part v0x564261f0f410_0, 3, 1;
|
||||||
|
L_0x564261f13020 .part v0x564261f0f280_0, 0, 1;
|
||||||
|
L_0x564261f13270 .part v0x564261f0f410_0, 3, 1;
|
||||||
|
L_0x564261f134a0 .part v0x564261f0f280_0, 1, 1;
|
||||||
|
L_0x564261f13590 .concat8 [ 1 1 1 0], L_0x564261f12d90, L_0x564261f13160, L_0x564261f13820;
|
||||||
|
L_0x564261f138e0 .part v0x564261f0f410_0, 3, 1;
|
||||||
|
L_0x564261f139d0 .part v0x564261f0f280_0, 2, 1;
|
||||||
|
L_0x564261f131d0 .part L_0x564261f0fd20, 0, 1;
|
||||||
|
L_0x564261f13d90 .part L_0x564261f10a00, 0, 1;
|
||||||
|
L_0x564261f140b0 .part L_0x564261f0fd20, 1, 1;
|
||||||
|
L_0x564261f141a0 .part L_0x564261f10a00, 1, 1;
|
||||||
|
L_0x564261f14540 .part L_0x564261f0fd20, 2, 1;
|
||||||
|
L_0x564261f14630 .part L_0x564261f10a00, 2, 1;
|
||||||
|
L_0x564261f148f0 .concat8 [ 1 1 1 1], L_0x564261f13c20, L_0x564261f14040, L_0x564261f14410, L_0x564261f14a30;
|
||||||
|
L_0x564261f14af0 .part L_0x564261f0fd20, 3, 1;
|
||||||
|
L_0x564261f14d80 .part L_0x564261f10a00, 3, 1;
|
||||||
|
L_0x564261f14fb0 .part L_0x564261f12620, 0, 1;
|
||||||
|
L_0x564261f152a0 .part L_0x564261f13590, 0, 1;
|
||||||
|
L_0x564261f15450 .part L_0x564261f12620, 1, 1;
|
||||||
|
L_0x564261f15700 .part L_0x564261f13590, 1, 1;
|
||||||
|
L_0x564261f15940 .part L_0x564261f12620, 2, 1;
|
||||||
|
L_0x564261f15c90 .part L_0x564261f13590, 2, 1;
|
||||||
|
L_0x564261f15dc0 .concat8 [ 1 1 1 1], L_0x564261f14e70, L_0x564261f153e0, L_0x564261f157f0, L_0x564261f160e0;
|
||||||
|
L_0x564261f161a0 .part L_0x564261f12620, 3, 1;
|
||||||
|
L_0x564261f16440 .part v0x564261f0f410_0, 0, 1;
|
||||||
|
L_0x564261f16720 .part v0x564261f0f410_0, 1, 1;
|
||||||
|
L_0x564261f168d0 .part v0x564261f0f410_0, 3, 1;
|
||||||
|
L_0x564261f16d30 .part L_0x564261f148f0, 0, 1;
|
||||||
|
L_0x564261f16e70 .part L_0x564261f15dc0, 0, 1;
|
||||||
|
L_0x564261f17230 .part L_0x564261f148f0, 1, 1;
|
||||||
|
L_0x564261f17320 .part L_0x564261f15dc0, 1, 1;
|
||||||
|
L_0x564261f177b0 .part L_0x564261f148f0, 2, 1;
|
||||||
|
L_0x564261f17930 .part L_0x564261f15dc0, 2, 1;
|
||||||
|
L_0x564261f17d00 .part L_0x564261f148f0, 3, 1;
|
||||||
|
L_0x564261f17da0 .part L_0x564261f15dc0, 3, 1;
|
||||||
|
L_0x564261f182b0 .part L_0x564261f12620, 4, 1;
|
||||||
|
L_0x564261f18410 .part L_0x564261f12620, 5, 1;
|
||||||
|
L_0x564261f18980 .part L_0x564261f12620, 6, 1;
|
||||||
|
LS_0x564261f18a20_0_0 .concat8 [ 1 1 1 1], L_0x564261f16bc0, L_0x564261f171c0, L_0x564261f17630, L_0x564261f17c90;
|
||||||
|
LS_0x564261f18a20_0_4 .concat8 [ 1 1 1 1], L_0x564261f180d0, L_0x564261f183a0, L_0x564261f18750, L_0x564261f18ff0;
|
||||||
|
L_0x564261f18a20 .concat8 [ 4 4 0 0], LS_0x564261f18a20_0_0, LS_0x564261f18a20_0_4;
|
||||||
|
L_0x564261f190b0 .part L_0x564261f12620, 7, 1;
|
||||||
|
.scope S_0x564261ee80a0;
|
||||||
|
T_0 ;
|
||||||
|
%vpi_call 2 17 "$dumpfile", "selector.vcd" {0 0 0};
|
||||||
|
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||||
|
%pushi/vec4 1, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f000_0, 0, 4;
|
||||||
|
%pushi/vec4 2, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f0e0_0, 0, 4;
|
||||||
|
%pushi/vec4 7, 0, 3;
|
||||||
|
%store/vec4 v0x564261f0f280_0, 0, 3;
|
||||||
|
%pushi/vec4 240, 0, 8;
|
||||||
|
%store/vec4 v0x564261f0f1b0_0, 0, 8;
|
||||||
|
%pushi/vec4 2, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f410_0, 0, 4;
|
||||||
|
%delay 5, 0;
|
||||||
|
%pushi/vec4 1, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f000_0, 0, 4;
|
||||||
|
%pushi/vec4 2, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f0e0_0, 0, 4;
|
||||||
|
%pushi/vec4 7, 0, 3;
|
||||||
|
%store/vec4 v0x564261f0f280_0, 0, 3;
|
||||||
|
%pushi/vec4 240, 0, 8;
|
||||||
|
%store/vec4 v0x564261f0f1b0_0, 0, 8;
|
||||||
|
%pushi/vec4 1, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f410_0, 0, 4;
|
||||||
|
%delay 5, 0;
|
||||||
|
%pushi/vec4 1, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f000_0, 0, 4;
|
||||||
|
%pushi/vec4 2, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f0e0_0, 0, 4;
|
||||||
|
%pushi/vec4 7, 0, 3;
|
||||||
|
%store/vec4 v0x564261f0f280_0, 0, 3;
|
||||||
|
%pushi/vec4 240, 0, 8;
|
||||||
|
%store/vec4 v0x564261f0f1b0_0, 0, 8;
|
||||||
|
%pushi/vec4 4, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f410_0, 0, 4;
|
||||||
|
%delay 5, 0;
|
||||||
|
%pushi/vec4 1, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f000_0, 0, 4;
|
||||||
|
%pushi/vec4 2, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f0e0_0, 0, 4;
|
||||||
|
%pushi/vec4 7, 0, 3;
|
||||||
|
%store/vec4 v0x564261f0f280_0, 0, 3;
|
||||||
|
%pushi/vec4 240, 0, 8;
|
||||||
|
%store/vec4 v0x564261f0f1b0_0, 0, 8;
|
||||||
|
%pushi/vec4 8, 0, 4;
|
||||||
|
%store/vec4 v0x564261f0f410_0, 0, 4;
|
||||||
|
%delay 5, 0;
|
||||||
|
%vpi_call 2 23 "$finish" {0 0 0};
|
||||||
|
%end;
|
||||||
|
.thread T_0;
|
||||||
|
# The file index is used to find the file name in the following table.
|
||||||
|
:file_names 4;
|
||||||
|
"N/A";
|
||||||
|
"<interactive>";
|
||||||
|
"selectorTB.v";
|
||||||
|
"selector.v";
|
||||||
@ -3,7 +3,7 @@ module selector (
|
|||||||
input [7:0] Y,
|
input [7:0] Y,
|
||||||
input [3:0] A, B,
|
input [3:0] A, B,
|
||||||
input [2:0] opCodeA,
|
input [2:0] opCodeA,
|
||||||
output [7:0] sO
|
output [7:0] s0
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [3:0] a0, b0, tempAB, tempYO;
|
wire [3:0] a0, b0, tempAB, tempYO;
|
||||||
@ -11,17 +11,19 @@ wire [7:0] y0;
|
|||||||
wire [2:0] op0;
|
wire [2:0] op0;
|
||||||
wire tempsO, temps;
|
wire tempsO, temps;
|
||||||
|
|
||||||
|
// Select signals for A
|
||||||
and a00 (a0[0], select[0], A[0]);
|
and a00 (a0[0], select[0], A[0]);
|
||||||
and a01 (a0[1], select[0], A[1]);
|
and a01 (a0[1], select[0], A[1]);
|
||||||
and a02 (a0[2], select[0], A[2]);
|
and a02 (a0[2], select[0], A[2]);
|
||||||
and a03 (a0[3], select[0], A[3]);
|
and a03 (a0[3], select[0], A[3]);
|
||||||
|
|
||||||
|
// Select signals for B
|
||||||
and b00 (b0[0], select[1], B[0]);
|
and b00 (b0[0], select[1], B[0]);
|
||||||
and b01 (b0[1], select[1], B[1]);
|
and b01 (b0[1], select[1], B[1]);
|
||||||
and b02 (b0[2], select[1], B[2]);
|
and b02 (b0[2], select[1], B[2]);
|
||||||
and b03 (b0[3], select[1], B[3]);
|
and b03 (b0[3], select[1], B[3]);
|
||||||
|
|
||||||
|
// Select signals for Y
|
||||||
and y00 (y0[0], select[2], Y[0]);
|
and y00 (y0[0], select[2], Y[0]);
|
||||||
and y01 (y0[1], select[2], Y[1]);
|
and y01 (y0[1], select[2], Y[1]);
|
||||||
and y02 (y0[2], select[2], Y[2]);
|
and y02 (y0[2], select[2], Y[2]);
|
||||||
@ -31,31 +33,36 @@ and y05 (y0[5], select[2], Y[5]);
|
|||||||
and y06 (y0[6], select[2], Y[6]);
|
and y06 (y0[6], select[2], Y[6]);
|
||||||
and y07 (y0[7], select[2], Y[7]);
|
and y07 (y0[7], select[2], Y[7]);
|
||||||
|
|
||||||
|
// Select signals for opCodeA
|
||||||
and op00 (op0[0], select[3], opCodeA[0]);
|
and op00 (op0[0], select[3], opCodeA[0]);
|
||||||
and op01 (op0[1], select[3], opCodeA[1]);
|
and op01 (op0[1], select[3], opCodeA[1]);
|
||||||
and op02 (op0[2], select[3], opCodeA[2]);
|
and op02 (op0[2], select[3], opCodeA[2]);
|
||||||
|
|
||||||
nor s01 (tempsO, select[0], select[1]);
|
// Combine A and B
|
||||||
nor s02 (temps, tempsO, select[3]);
|
|
||||||
|
|
||||||
or or1 (tempAB[0], a0[0], b0[0]);
|
or or1 (tempAB[0], a0[0], b0[0]);
|
||||||
or or2 (tempAB[1], a0[1], b0[1]);
|
or or2 (tempAB[1], a0[1], b0[1]);
|
||||||
or or3 (tempAB[2], a0[2], b0[2]);
|
or or3 (tempAB[2], a0[2], b0[2]);
|
||||||
or or4 (tempAB[3], a0[3], b0[3]);
|
or or4 (tempAB[3], a0[3], b0[3]);
|
||||||
|
|
||||||
|
// Combine Y and opCodeA
|
||||||
or or5 (tempYO[0], y0[0], op0[0]);
|
or or5 (tempYO[0], y0[0], op0[0]);
|
||||||
or or6 (tempYO[1], y0[1], op0[1]);
|
or or6 (tempYO[1], y0[1], op0[1]);
|
||||||
or or7 (tempYO[2], y0[2], op0[2]);
|
or or7 (tempYO[2], y0[2], op0[2]);
|
||||||
or or8 (tempYO[3], y0[3], 1'b0);
|
or or8 (tempYO[3], y0[3], 1'b0);
|
||||||
|
|
||||||
and and00 (s0[0], tempAB[0], tempYO[0]);
|
// NOR for select logic
|
||||||
and and00 (s0[1], tempAB[1], tempYO[1]);
|
nor s01 (tempsO, select[0], select[1]);
|
||||||
and and00 (s0[2], tempAB[2], tempYO[2]);
|
nor s02 (temps, tempsO, select[3]);
|
||||||
and and00 (s0[3], tempAB[3], tempYO[3]);
|
|
||||||
and and04 (s0[4], y0[4], temps);
|
|
||||||
and and05 (s0[5], y0[5], temps);
|
|
||||||
and and06 (s0[6], y0[6], temps);
|
|
||||||
and and07 (s0[7], y0[7], temps);
|
|
||||||
|
|
||||||
|
// Final s0 connections
|
||||||
|
or or9 (s0[0], tempAB[0], tempYO[0]);
|
||||||
|
or or10 (s0[1], tempAB[1], tempYO[1]);
|
||||||
|
or or11 (s0[2], tempAB[2], tempYO[2]);
|
||||||
|
or or12 (s0[3], tempAB[3], tempYO[3]);
|
||||||
|
|
||||||
|
and and13 (s0[4], y0[4], temps);
|
||||||
|
and and14 (s0[5], y0[5], temps);
|
||||||
|
and and15 (s0[6], y0[6], temps);
|
||||||
|
and and16 (s0[7], y0[7], temps);
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|||||||
85
project0.2/selector.vcd
Normal file
85
project0.2/selector.vcd
Normal file
@ -0,0 +1,85 @@
|
|||||||
|
$date
|
||||||
|
Wed Jan 8 01:04:48 2025
|
||||||
|
$end
|
||||||
|
$version
|
||||||
|
Icarus Verilog
|
||||||
|
$end
|
||||||
|
$timescale
|
||||||
|
1s
|
||||||
|
$end
|
||||||
|
$scope module selectorTB $end
|
||||||
|
$var wire 8 ! s0 [7:0] $end
|
||||||
|
$var reg 4 " A [3:0] $end
|
||||||
|
$var reg 4 # B [3:0] $end
|
||||||
|
$var reg 8 $ Y [7:0] $end
|
||||||
|
$var reg 3 % opCodeA [2:0] $end
|
||||||
|
$var reg 4 & select [3:0] $end
|
||||||
|
$scope module uut $end
|
||||||
|
$var wire 4 ' A [3:0] $end
|
||||||
|
$var wire 4 ( B [3:0] $end
|
||||||
|
$var wire 8 ) Y [7:0] $end
|
||||||
|
$var wire 3 * opCodeA [2:0] $end
|
||||||
|
$var wire 4 + select [3:0] $end
|
||||||
|
$var wire 1 , temps $end
|
||||||
|
$var wire 1 - tempsO $end
|
||||||
|
$var wire 8 . y0 [7:0] $end
|
||||||
|
$var wire 4 / tempYO [3:0] $end
|
||||||
|
$var wire 4 0 tempAB [3:0] $end
|
||||||
|
$var wire 8 1 s0 [7:0] $end
|
||||||
|
$var wire 3 2 op0 [2:0] $end
|
||||||
|
$var wire 4 3 b0 [3:0] $end
|
||||||
|
$var wire 4 4 a0 [3:0] $end
|
||||||
|
$upscope $end
|
||||||
|
$upscope $end
|
||||||
|
$enddefinitions $end
|
||||||
|
#0
|
||||||
|
$dumpvars
|
||||||
|
b0 4
|
||||||
|
b10 3
|
||||||
|
b0 2
|
||||||
|
b10 1
|
||||||
|
b10 0
|
||||||
|
b0 /
|
||||||
|
b0 .
|
||||||
|
0-
|
||||||
|
1,
|
||||||
|
b10 +
|
||||||
|
b111 *
|
||||||
|
bz )
|
||||||
|
b10 (
|
||||||
|
b1 '
|
||||||
|
b10 &
|
||||||
|
b111 %
|
||||||
|
b11110000 $
|
||||||
|
b10 #
|
||||||
|
b1 "
|
||||||
|
b10 !
|
||||||
|
$end
|
||||||
|
#5
|
||||||
|
b1 !
|
||||||
|
b1 1
|
||||||
|
b1 0
|
||||||
|
b1 4
|
||||||
|
b0 3
|
||||||
|
b1 &
|
||||||
|
b1 +
|
||||||
|
#10
|
||||||
|
b0xxxx !
|
||||||
|
b0xxxx 1
|
||||||
|
b0 0
|
||||||
|
bx /
|
||||||
|
0,
|
||||||
|
b0 4
|
||||||
|
bx .
|
||||||
|
1-
|
||||||
|
b100 &
|
||||||
|
b100 +
|
||||||
|
#15
|
||||||
|
b111 !
|
||||||
|
b111 1
|
||||||
|
b111 /
|
||||||
|
b0 .
|
||||||
|
b111 2
|
||||||
|
b1000 &
|
||||||
|
b1000 +
|
||||||
|
#20
|
||||||
26
project0.2/selectorTB.v
Normal file
26
project0.2/selectorTB.v
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
module selectorTB();
|
||||||
|
|
||||||
|
reg [3:0] select, A, B;
|
||||||
|
reg [7:0] Y;
|
||||||
|
reg [2:0] opCodeA;
|
||||||
|
wire [7:0] s0;
|
||||||
|
|
||||||
|
selector uut (
|
||||||
|
.select(select),
|
||||||
|
.A(A),
|
||||||
|
.B(B),
|
||||||
|
.opCodeA(opCodeA),
|
||||||
|
.s0(s0)
|
||||||
|
);
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
$dumpfile("selector.vcd");
|
||||||
|
$dumpvars;
|
||||||
|
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0010; #5;
|
||||||
|
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0001; #5;
|
||||||
|
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0100; #5;
|
||||||
|
A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b1000; #5;
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
x
Reference in New Issue
Block a user