27 lines
631 B
Verilog
27 lines
631 B
Verilog
module selectorTB();
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reg [3:0] select, A, B;
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reg [7:0] Y;
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reg [2:0] opCodeA;
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wire [7:0] s0;
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selector uut (
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.select(select),
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.A(A),
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.B(B),
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.opCodeA(opCodeA),
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.s0(s0)
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);
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initial begin
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$dumpfile("selector.vcd");
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$dumpvars;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0010; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0001; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0100; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b1000; #5;
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$finish;
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end
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endmodule
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