33 lines
678 B
Verilog
33 lines
678 B
Verilog
module PU (
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input A, // Dividend bit
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input B, // Divisor bit
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input Cin, // Carry input
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input S, // Select input for the mux
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output Y, // Output of the PU
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output COut // Carry output from the full adder
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);
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wire Sum, notB;
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// Invert B for subtraction
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not n1 (notB, B);
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// Full adder performs A - B + Cin
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fulladder f1 (
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.A(A),
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.B(notB),
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.Carry(Cin),
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.Sum(Sum),
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.CarryO(COut)
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);
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// 2:1 multiplexer to select between A and Sum
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mux2 m1 (
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.A0(A), // Input 0 of mux
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.A1(Sum), // Input 1 of mux
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.S(S), // Select line
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.Y(Y) // Output of the mux
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);
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endmodule
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