59 lines
1.2 KiB
Verilog
59 lines
1.2 KiB
Verilog
module divider4 (
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input [3:0] Dividend, // 4-bit dividend
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input [1:0] Divisor, // 2-bit divisor
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output [3:0] Quotient, // 4-bit quotient
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output [2:0] Remainder // 3-bit remainder
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);
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wire [3:0] Carry; // Carry wires between PUs
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wire [3:0] Y; // Intermediate PU outputs
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wire S0, S1; // Select signals based on division logic
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// Calculate select signals based on carry outputs
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assign S0 = Carry[3]; // First select signal
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assign S1 = Carry[2]; // Second select signal
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// Row 1
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PU PU1 (
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.A(Dividend[3]),
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.B(Divisor[1]),
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.Cin(1'b0), // Initial carry input is 0
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.S(S0),
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.Y(Y[3]),
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.COut(Carry[3])
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);
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PU PU2 (
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.A(Dividend[2]),
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.B(Divisor[1]),
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.Cin(Carry[3]),
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.S(S0),
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.Y(Y[2]),
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.COut(Carry[2])
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);
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// Row 2
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PU PU3 (
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.A(Dividend[1]),
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.B(Divisor[0]),
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.Cin(Carry[2]),
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.S(S1),
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.Y(Y[1]),
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.COut(Carry[1])
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);
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PU PU4 (
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.A(Dividend[0]),
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.B(Divisor[0]),
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.Cin(Carry[1]),
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.S(S1),
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.Y(Y[0]),
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.COut(Carry[0])
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);
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// Assign outputs
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assign Quotient = Y; // Output of the PUs is the quotient
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assign Remainder = Carry; // Final carry values are the remainder
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endmodule
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