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xorGate

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This commit is contained in:
k0rrluna
2024-12-09 22:57:42 +03:00
parent 6f6f491135
commit 2acbfd9d8d
29 changed files with 1478 additions and 1231 deletions
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26
iverilog/tobb/lab2/Fulladder.v
View File

@@ -1,26 +0,0 @@
module Fulladder (
input A,
input B,
input Cin,
output S,
output Cout
);
wire AxB, AnB1, AnB2;
halfadder h1 (
.A(A),
.B(B),
.Sum(AxB),
.Carry(AnB2)
);
halfadder h2 (
.A(AxB),
.B(Cin),
.Sum(S),
.Carry(AnB1)
);
or o1 (.Y(Cout), .A(AnB1), .B(AnB2));
endmodule

168
iverilog/tobb/lab2/fdmp.vcd
View File

@@ -1,84 +1,84 @@
$date
Tue Oct 8 14:05:40 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fulladdertb $end
$var wire 1 ! w2 $end
$var wire 1 " w1 $end
$var reg 1 # r1 $end
$var reg 1 $ r2 $end
$var reg 1 % r3 $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 % Cin $end
$var wire 1 ! Cout $end
$var wire 1 " S $end
$var wire 1 & AxB $end
$var wire 1 ' AnB2 $end
$var wire 1 ( AnB1 $end
$scope module h1 $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 ' C $end
$var wire 1 & S $end
$upscope $end
$scope module h2 $end
$var wire 1 & A $end
$var wire 1 % B $end
$var wire 1 ( C $end
$var wire 1 " S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0(
0'
0&
0%
0$
0#
0"
0!
$end
#10
1"
1%
#20
1&
0%
1$
#30
1!
0"
1(
1%
#40
0!
1"
0(
0%
0$
1#
#50
1!
0"
1(
1%
#60
0(
0&
1'
0%
1$
#70
1"
1%
#80
$date
Sun Dec 8 20:51:56 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module fulladdertb $end
$var wire 1 ! w2 $end
$var wire 1 " w1 $end
$var reg 1 # r1 $end
$var reg 1 $ r2 $end
$var reg 1 % r3 $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 % Cin $end
$var wire 1 ! Cout $end
$var wire 1 " S $end
$var wire 1 & AxB $end
$var wire 1 ' AnB2 $end
$var wire 1 ( AnB1 $end
$scope module h1 $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 ' C $end
$var wire 1 & S $end
$upscope $end
$scope module h2 $end
$var wire 1 & A $end
$var wire 1 % B $end
$var wire 1 ( C $end
$var wire 1 " S $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0(
0'
0&
0%
0$
0#
0"
0!
$end
#10
1"
1%
#20
1&
0%
1$
#30
1!
0"
1(
1%
#40
0!
1"
0(
0%
0$
1#
#50
1!
0"
1(
1%
#60
0(
0&
1'
0%
1$
#70
1"
1%
#80

254
iverilog/tobb/lab2/fulladder
View File

@@ -1,127 +1,127 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x557fe3a27ae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
.timescale 0 0;
v0x557fe3a3b940_0 .var "r1", 0 0;
v0x557fe3a3ba30_0 .var "r2", 0 0;
v0x557fe3a3bb40_0 .var "r3", 0 0;
v0x557fe3a3bc30_0 .net "w1", 0 0, L_0x557fe3a3bf40; 1 drivers
v0x557fe3a3bd20_0 .net "w2", 0 0, L_0x557fe3a3c1a0; 1 drivers
S_0x557fe3a27c70 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_0x557fe3a27ae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout";
L_0x557fe3a3c1a0 .functor OR 1, L_0x557fe3a3c080, L_0x557fe3a3be80, C4<0>, C4<0>;
v0x557fe3a3b290_0 .net "A", 0 0, v0x557fe3a3b940_0; 1 drivers
v0x557fe3a3b350_0 .net "AnB1", 0 0, L_0x557fe3a3c080; 1 drivers
v0x557fe3a3b420_0 .net "AnB2", 0 0, L_0x557fe3a3be80; 1 drivers
v0x557fe3a3b520_0 .net "AxB", 0 0, L_0x557fe3a3be10; 1 drivers
v0x557fe3a3b610_0 .net "B", 0 0, v0x557fe3a3ba30_0; 1 drivers
v0x557fe3a3b700_0 .net "Cin", 0 0, v0x557fe3a3bb40_0; 1 drivers
v0x557fe3a3b7a0_0 .net "Cout", 0 0, L_0x557fe3a3c1a0; alias, 1 drivers
v0x557fe3a3b840_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
S_0x557fe3a22df0 .scope module, "h1" "halfadder" 3 9, 4 1 0, S_0x557fe3a27c70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3be10 .functor XOR 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<0>, C4<0>;
L_0x557fe3a3be80 .functor AND 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<1>, C4<1>;
v0x557fe3a23070_0 .net "A", 0 0, v0x557fe3a3b940_0; alias, 1 drivers
v0x557fe3a3a970_0 .net "B", 0 0, v0x557fe3a3ba30_0; alias, 1 drivers
v0x557fe3a3aa30_0 .net "C", 0 0, L_0x557fe3a3be80; alias, 1 drivers
v0x557fe3a3ab00_0 .net "S", 0 0, L_0x557fe3a3be10; alias, 1 drivers
S_0x557fe3a3ac70 .scope module, "h2" "halfadder" 3 10, 4 1 0, S_0x557fe3a27c70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x557fe3a3bf40 .functor XOR 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<0>, C4<0>;
L_0x557fe3a3c080 .functor AND 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<1>, C4<1>;
v0x557fe3a3aee0_0 .net "A", 0 0, L_0x557fe3a3be10; alias, 1 drivers
v0x557fe3a3afb0_0 .net "B", 0 0, v0x557fe3a3bb40_0; alias, 1 drivers
v0x557fe3a3b050_0 .net "C", 0 0, L_0x557fe3a3c080; alias, 1 drivers
v0x557fe3a3b120_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
.scope S_0x557fe3a27ae0;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3b940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
%delay 10, 0;
%vpi_call 2 25 "$display", v0x557fe3a3bc30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x557fe3a3bd20_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"fulladdertb.v";
"fulladder.v";
"halfadder.v";
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56122b07fae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
.timescale 0 0;
v0x56122b093940_0 .var "r1", 0 0;
v0x56122b093a30_0 .var "r2", 0 0;
v0x56122b093b40_0 .var "r3", 0 0;
v0x56122b093c30_0 .net "w1", 0 0, L_0x56122b093f40; 1 drivers
v0x56122b093d20_0 .net "w2", 0 0, L_0x56122b0941a0; 1 drivers
S_0x56122b07fc70 .scope module, "uut" "fulladder" 2 6, 3 1 0, S_0x56122b07fae0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout";
L_0x56122b0941a0 .functor OR 1, L_0x56122b094080, L_0x56122b093e80, C4<0>, C4<0>;
v0x56122b093290_0 .net "A", 0 0, v0x56122b093940_0; 1 drivers
v0x56122b093350_0 .net "AnB1", 0 0, L_0x56122b094080; 1 drivers
v0x56122b093420_0 .net "AnB2", 0 0, L_0x56122b093e80; 1 drivers
v0x56122b093520_0 .net "AxB", 0 0, L_0x56122b093e10; 1 drivers
v0x56122b093610_0 .net "B", 0 0, v0x56122b093a30_0; 1 drivers
v0x56122b093700_0 .net "Cin", 0 0, v0x56122b093b40_0; 1 drivers
v0x56122b0937a0_0 .net "Cout", 0 0, L_0x56122b0941a0; alias, 1 drivers
v0x56122b093840_0 .net "S", 0 0, L_0x56122b093f40; alias, 1 drivers
S_0x56122b07adf0 .scope module, "h1" "halfadder" 3 11, 4 1 0, S_0x56122b07fc70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x56122b093e10 .functor XOR 1, v0x56122b093940_0, v0x56122b093a30_0, C4<0>, C4<0>;
L_0x56122b093e80 .functor AND 1, v0x56122b093940_0, v0x56122b093a30_0, C4<1>, C4<1>;
v0x56122b07b070_0 .net "A", 0 0, v0x56122b093940_0; alias, 1 drivers
v0x56122b092970_0 .net "B", 0 0, v0x56122b093a30_0; alias, 1 drivers
v0x56122b092a30_0 .net "C", 0 0, L_0x56122b093e80; alias, 1 drivers
v0x56122b092b00_0 .net "S", 0 0, L_0x56122b093e10; alias, 1 drivers
S_0x56122b092c70 .scope module, "h2" "halfadder" 3 13, 4 1 0, S_0x56122b07fc70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_0x56122b093f40 .functor XOR 1, L_0x56122b093e10, v0x56122b093b40_0, C4<0>, C4<0>;
L_0x56122b094080 .functor AND 1, L_0x56122b093e10, v0x56122b093b40_0, C4<1>, C4<1>;
v0x56122b092ee0_0 .net "A", 0 0, L_0x56122b093e10; alias, 1 drivers
v0x56122b092fb0_0 .net "B", 0 0, v0x56122b093b40_0; alias, 1 drivers
v0x56122b093050_0 .net "C", 0 0, L_0x56122b094080; alias, 1 drivers
v0x56122b093120_0 .net "S", 0 0, L_0x56122b093f40; alias, 1 drivers
.scope S_0x56122b07fae0;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093940_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093a30_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56122b093b40_0, 0, 1;
%delay 10, 0;
%vpi_call 2 25 "$display", v0x56122b093c30_0 {0 0 0};
%vpi_call 2 26 "$display", v0x56122b093d20_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"fulladdertb.v";
"fulladder.v";
"halfadder.v";

16
iverilog/tobb/lab2/fulladder.v Normal file
View File

@@ -0,0 +1,16 @@
module fulladder (
input A,
input B,
input Cin,
output S,
output Cout
);
wire AxB, AnB1, AnB2;
halfadder h1 (A,B,AxB,AnB2);
halfadder h2 (AxB,Cin,S,AnB1);
or o1 (Cout,AnB1,AnB2);
endmodule

2
iverilog/tobb/lab2/fulladdertb.v
View File

@@ -3,7 +3,7 @@ module fulladdertb ();
reg r1, r2, r3;
wire w1, w2;
FullAdder uut(
fulladder uut(
.A(r1),
.B(r2),
.Cin(r3),