iverilog
This commit is contained in:
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32
iverilog/lab2/HammingDistance/ham.vcd
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32
iverilog/lab2/HammingDistance/ham.vcd
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@ -0,0 +1,32 @@
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$date
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Tue Oct 8 14:33:58 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module htb $end
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$var reg 8 ! value1 [7:0] $end
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$var reg 8 " value2 [7:0] $end
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$scope module uut $end
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$var wire 8 # value1 [7:0] $end
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$var wire 8 $ value2 [7:0] $end
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$var reg 4 % hammingValue [3:0] $end
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$var integer 32 & i [31:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b1000 &
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b0 %
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bz $
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bz #
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b10111111 "
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b10110000 !
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$end
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#10
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b10111111 !
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#20
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83
iverilog/lab2/HammingDistance/hamming
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83
iverilog/lab2/HammingDistance/hamming
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@ -0,0 +1,83 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x555b2f00bc50 .scope module, "htb" "htb" 2 1;
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.timescale 0 0;
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v0x555b2f01d190_0 .var "value1", 7 0;
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v0x555b2f01d270_0 .var "value2", 7 0;
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S_0x555b2f00bde0 .scope module, "uut" "hamming" 2 7, 3 1 0, S_0x555b2f00bc50;
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.timescale 0 0;
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.port_info 0 /INPUT 8 "value1";
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.port_info 1 /INPUT 8 "value2";
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.port_info 2 /OUTPUT 4 "hammingValue";
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v0x555b2efd27f0_0 .var "hammingValue", 3 0;
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v0x555b2efd2c00_0 .var/i "i", 31 0;
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o0x7f3f4267c078 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
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v0x555b2f01cf70_0 .net "value1", 7 0, o0x7f3f4267c078; 0 drivers
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o0x7f3f4267c0a8 .functor BUFZ 8, C4<zzzzzzzz>; HiZ drive
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v0x555b2f01d030_0 .net "value2", 7 0, o0x7f3f4267c0a8; 0 drivers
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E_0x555b2f00a130 .event edge, v0x555b2f01cf70_0, v0x555b2f01d030_0, v0x555b2efd27f0_0;
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.scope S_0x555b2f00bde0;
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T_0 ;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x555b2efd2c00_0, 0, 32;
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%end;
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.thread T_0;
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.scope S_0x555b2f00bde0;
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T_1 ;
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%wait E_0x555b2f00a130;
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%pushi/vec4 0, 0, 4;
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%store/vec4 v0x555b2efd27f0_0, 0, 4;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x555b2efd2c00_0, 0, 32;
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T_1.0 ;
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%load/vec4 v0x555b2efd2c00_0;
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%cmpi/s 8, 0, 32;
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%jmp/0xz T_1.1, 5;
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%load/vec4 v0x555b2f01cf70_0;
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%load/vec4 v0x555b2efd2c00_0;
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%part/s 1;
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%load/vec4 v0x555b2f01d030_0;
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%load/vec4 v0x555b2efd2c00_0;
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%part/s 1;
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%cmp/e;
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%jmp/0xz T_1.2, 4;
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%load/vec4 v0x555b2efd27f0_0;
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%addi 1, 0, 4;
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%store/vec4 v0x555b2efd27f0_0, 0, 4;
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T_1.2 ;
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%load/vec4 v0x555b2efd2c00_0;
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%addi 1, 0, 32;
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%store/vec4 v0x555b2efd2c00_0, 0, 32;
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%jmp T_1.0;
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T_1.1 ;
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%jmp T_1;
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.thread T_1, $push;
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.scope S_0x555b2f00bc50;
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T_2 ;
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%vpi_call 2 12 "$dumpfile", "ham.vcd" {0 0 0};
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%vpi_call 2 13 "$dumpvars" {0 0 0};
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%pushi/vec4 176, 0, 8;
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%store/vec4 v0x555b2f01d190_0, 0, 8;
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%pushi/vec4 191, 0, 8;
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%store/vec4 v0x555b2f01d270_0, 0, 8;
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%delay 10, 0;
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%pushi/vec4 191, 0, 8;
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%store/vec4 v0x555b2f01d190_0, 0, 8;
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%pushi/vec4 191, 0, 8;
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%store/vec4 v0x555b2f01d270_0, 0, 8;
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%delay 10, 0;
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%end;
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.thread T_2;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"htb.v";
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"hamming.v";
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17
iverilog/lab2/HammingDistance/hamming.v
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17
iverilog/lab2/HammingDistance/hamming.v
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module hamming (
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input[7:0] value1,
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input[7:0] value2,
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output reg[3:0] hammingValue
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);
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integer i = 0;
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always @(*) begin
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hammingValue = 0;
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for(i = 0; i < 8; i = i+1) begin
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if (value1[i] == value2[i]) begin
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hammingValue = hammingValue + 1;
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end
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end
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end
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endmodule
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19
iverilog/lab2/HammingDistance/htb.v
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19
iverilog/lab2/HammingDistance/htb.v
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module htb ();
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reg [7:0] value1;
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reg [7:0] value2;
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wire [3:0] hammingValue;
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hamming uut (
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.value1(value1),
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.value2(value2),
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.hammingValue(hammingValue)
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);
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initial begin
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$dumpfile("ham.vcd");
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$dumpvars;
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value1 = 8'hB0; value2 = 8'hBF; #10;
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value1 = 8'hBF; value2 = 8'hBF; #10;
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end
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endmodule
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84
iverilog/lab2/fdmp.vcd
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84
iverilog/lab2/fdmp.vcd
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@ -0,0 +1,84 @@
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$date
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Tue Oct 8 14:05:40 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module fulladdertb $end
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$var wire 1 ! w2 $end
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$var wire 1 " w1 $end
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$var reg 1 # r1 $end
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$var reg 1 $ r2 $end
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$var reg 1 % r3 $end
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$scope module uut $end
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$var wire 1 # A $end
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$var wire 1 $ B $end
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$var wire 1 % Cin $end
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$var wire 1 ! Cout $end
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$var wire 1 " S $end
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$var wire 1 & AxB $end
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$var wire 1 ' AnB2 $end
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$var wire 1 ( AnB1 $end
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$scope module h1 $end
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$var wire 1 # A $end
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$var wire 1 $ B $end
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$var wire 1 ' C $end
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$var wire 1 & S $end
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$upscope $end
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$scope module h2 $end
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$var wire 1 & A $end
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$var wire 1 % B $end
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$var wire 1 ( C $end
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$var wire 1 " S $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0(
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0'
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0&
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0%
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0$
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0#
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0"
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0!
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$end
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#10
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1"
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1%
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#20
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1&
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0%
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1$
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#30
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1!
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0"
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1(
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1%
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#40
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0!
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1"
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0(
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0%
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0$
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1#
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#50
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1!
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0"
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1(
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1%
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#60
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0(
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0&
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1'
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0%
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1$
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#70
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1"
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1%
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#80
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127
iverilog/lab2/fulladder
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127
iverilog/lab2/fulladder
Normal file
@ -0,0 +1,127 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x557fe3a27ae0 .scope module, "fulladdertb" "fulladdertb" 2 1;
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.timescale 0 0;
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v0x557fe3a3b940_0 .var "r1", 0 0;
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v0x557fe3a3ba30_0 .var "r2", 0 0;
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v0x557fe3a3bb40_0 .var "r3", 0 0;
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v0x557fe3a3bc30_0 .net "w1", 0 0, L_0x557fe3a3bf40; 1 drivers
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v0x557fe3a3bd20_0 .net "w2", 0 0, L_0x557fe3a3c1a0; 1 drivers
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S_0x557fe3a27c70 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_0x557fe3a27ae0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /INPUT 1 "Cin";
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.port_info 3 /OUTPUT 1 "S";
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.port_info 4 /OUTPUT 1 "Cout";
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L_0x557fe3a3c1a0 .functor OR 1, L_0x557fe3a3c080, L_0x557fe3a3be80, C4<0>, C4<0>;
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v0x557fe3a3b290_0 .net "A", 0 0, v0x557fe3a3b940_0; 1 drivers
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v0x557fe3a3b350_0 .net "AnB1", 0 0, L_0x557fe3a3c080; 1 drivers
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v0x557fe3a3b420_0 .net "AnB2", 0 0, L_0x557fe3a3be80; 1 drivers
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v0x557fe3a3b520_0 .net "AxB", 0 0, L_0x557fe3a3be10; 1 drivers
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v0x557fe3a3b610_0 .net "B", 0 0, v0x557fe3a3ba30_0; 1 drivers
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v0x557fe3a3b700_0 .net "Cin", 0 0, v0x557fe3a3bb40_0; 1 drivers
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v0x557fe3a3b7a0_0 .net "Cout", 0 0, L_0x557fe3a3c1a0; alias, 1 drivers
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v0x557fe3a3b840_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
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S_0x557fe3a22df0 .scope module, "h1" "halfadder" 3 9, 4 1 0, S_0x557fe3a27c70;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
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.port_info 1 /INPUT 1 "B";
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.port_info 2 /OUTPUT 1 "S";
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.port_info 3 /OUTPUT 1 "C";
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L_0x557fe3a3be10 .functor XOR 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<0>, C4<0>;
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L_0x557fe3a3be80 .functor AND 1, v0x557fe3a3b940_0, v0x557fe3a3ba30_0, C4<1>, C4<1>;
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v0x557fe3a23070_0 .net "A", 0 0, v0x557fe3a3b940_0; alias, 1 drivers
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v0x557fe3a3a970_0 .net "B", 0 0, v0x557fe3a3ba30_0; alias, 1 drivers
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v0x557fe3a3aa30_0 .net "C", 0 0, L_0x557fe3a3be80; alias, 1 drivers
|
||||
v0x557fe3a3ab00_0 .net "S", 0 0, L_0x557fe3a3be10; alias, 1 drivers
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S_0x557fe3a3ac70 .scope module, "h2" "halfadder" 3 10, 4 1 0, S_0x557fe3a27c70;
|
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.timescale 0 0;
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.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
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.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0x557fe3a3bf40 .functor XOR 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<0>, C4<0>;
|
||||
L_0x557fe3a3c080 .functor AND 1, L_0x557fe3a3be10, v0x557fe3a3bb40_0, C4<1>, C4<1>;
|
||||
v0x557fe3a3aee0_0 .net "A", 0 0, L_0x557fe3a3be10; alias, 1 drivers
|
||||
v0x557fe3a3afb0_0 .net "B", 0 0, v0x557fe3a3bb40_0; alias, 1 drivers
|
||||
v0x557fe3a3b050_0 .net "C", 0 0, L_0x557fe3a3c080; alias, 1 drivers
|
||||
v0x557fe3a3b120_0 .net "S", 0 0, L_0x557fe3a3bf40; alias, 1 drivers
|
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.scope S_0x557fe3a27ae0;
|
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T_0 ;
|
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%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3b940_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3ba30_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x557fe3a3bb40_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 25 "$display", v0x557fe3a3bc30_0 {0 0 0};
|
||||
%vpi_call 2 26 "$display", v0x557fe3a3bd20_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 5;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"fulladdertb.v";
|
||||
"fulladder.v";
|
||||
"halfadder.v";
|
||||
13
iverilog/lab2/fulladder.v
Normal file
13
iverilog/lab2/fulladder.v
Normal file
@ -0,0 +1,13 @@
|
||||
module fullAdder (
|
||||
input A,
|
||||
input B,
|
||||
input Cin,
|
||||
output S,
|
||||
output Cout
|
||||
);
|
||||
wire AxB, AnB1, AnB2;
|
||||
halfadder h1(A, B, AxB, AnB2);
|
||||
halfadder h2(AxB, Cin, S, AnB1);
|
||||
|
||||
or o1(Cout, AnB1, AnB2);
|
||||
endmodule
|
||||
29
iverilog/lab2/fulladdertb.v
Normal file
29
iverilog/lab2/fulladdertb.v
Normal file
@ -0,0 +1,29 @@
|
||||
module fulladdertb ();
|
||||
|
||||
reg r1, r2, r3;
|
||||
wire w1, w2;
|
||||
|
||||
fullAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.Cin(r3),
|
||||
.S(w1),
|
||||
.Cout(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("fdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; r3 = 0; #10
|
||||
r1 = 0; r2 = 0; r3 = 1; #10
|
||||
r1 = 0; r2 = 1; r3 = 0; #10
|
||||
r1 = 0; r2 = 1; r3 = 1; #10
|
||||
r1 = 1; r2 = 0; r3 = 0; #10
|
||||
r1 = 1; r2 = 0; r3 = 1; #10
|
||||
r1 = 1; r2 = 1; r3 = 0; #10
|
||||
r1 = 1; r2 = 1; r3 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
||||
40
iverilog/lab2/hadmp.vcd
Normal file
40
iverilog/lab2/hadmp.vcd
Normal file
@ -0,0 +1,40 @@
|
||||
$date
|
||||
Tue Oct 8 10:23:08 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module halfaddertb $end
|
||||
$var wire 1 ! S $end
|
||||
$var wire 1 " C $end
|
||||
$var reg 1 # A $end
|
||||
$var reg 1 $ B $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 " C $end
|
||||
$var wire 1 ! S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
1$
|
||||
#20
|
||||
0$
|
||||
1#
|
||||
#30
|
||||
0!
|
||||
1"
|
||||
1$
|
||||
#40
|
||||
59
iverilog/lab2/halfadder
Normal file
59
iverilog/lab2/halfadder
Normal file
@ -0,0 +1,59 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5583f1e33260 .scope module, "halfaddertb" "halfaddertb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5583f1e44440_0 .var "A", 0 0;
|
||||
v0x5583f1e44500_0 .var "B", 0 0;
|
||||
v0x5583f1e445d0_0 .net "C", 0 0, L_0x5583f1e44900; 1 drivers
|
||||
v0x5583f1e446d0_0 .net "S", 0 0, L_0x5583f1e447a0; 1 drivers
|
||||
S_0x5583f1e333f0 .scope module, "uut" "halfadder" 2 5, 3 1 0, S_0x5583f1e33260;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0x5583f1e447a0 .functor XOR 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<0>, C4<0>;
|
||||
L_0x5583f1e44900 .functor AND 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<1>, C4<1>;
|
||||
v0x5583f1dfbc00_0 .net "A", 0 0, v0x5583f1e44440_0; 1 drivers
|
||||
v0x5583f1e44140_0 .net "B", 0 0, v0x5583f1e44500_0; 1 drivers
|
||||
v0x5583f1e44200_0 .net "C", 0 0, L_0x5583f1e44900; alias, 1 drivers
|
||||
v0x5583f1e442d0_0 .net "S", 0 0, L_0x5583f1e447a0; alias, 1 drivers
|
||||
.scope S_0x5583f1e33260;
|
||||
T_0 ;
|
||||
%vpi_call 2 10 "$dumpfile", "hadmp.vcd" {0 0 0};
|
||||
%vpi_call 2 11 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"halfaddertb.v";
|
||||
"halfadder.v";
|
||||
9
iverilog/lab2/halfadder.v
Normal file
9
iverilog/lab2/halfadder.v
Normal file
@ -0,0 +1,9 @@
|
||||
module halfadder (
|
||||
input A,
|
||||
input B,
|
||||
output S,
|
||||
output C
|
||||
);
|
||||
xor x1(S, A, B);
|
||||
and a1(C, A, B);
|
||||
endmodule
|
||||
18
iverilog/lab2/halfaddertb.v
Normal file
18
iverilog/lab2/halfaddertb.v
Normal file
@ -0,0 +1,18 @@
|
||||
module halfaddertb ();
|
||||
reg A, B;
|
||||
wire S, C;
|
||||
|
||||
halfadder uut(
|
||||
.A(A), .B(B), .S(S), .C(C)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("hadmp.vcd");
|
||||
$dumpvars;
|
||||
A = 1'b0; B = 1'b0; #10;
|
||||
A = 1'b0; B = 1'b1; #10;
|
||||
A = 1'b1; B = 1'b0; #10;
|
||||
A = 1'b1; B = 1'b1; #10;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user