41 lines
423 B
Plaintext
41 lines
423 B
Plaintext
$date
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Tue Oct 8 10:23:08 2024
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module halfaddertb $end
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$var wire 1 ! S $end
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$var wire 1 " C $end
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$var reg 1 # A $end
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$var reg 1 $ B $end
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$scope module uut $end
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$var wire 1 # A $end
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$var wire 1 $ B $end
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$var wire 1 " C $end
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$var wire 1 ! S $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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0$
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0#
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0"
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0!
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$end
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#10
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1!
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1$
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#20
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0$
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1#
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#30
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0!
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1"
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1$
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#40
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