17 lines
313 B
Verilog
17 lines
313 B
Verilog
module hamming (
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input[7:0] value1,
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input[7:0] value2,
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output reg[3:0] hammingValue
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);
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integer i = 0;
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always @(*) begin
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hammingValue = 0;
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for(i = 0; i < 8; i = i+1) begin
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if (value1[i] == value2[i]) begin
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hammingValue = hammingValue + 1;
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end
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end
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end
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endmodule |