29 lines
499 B
Verilog
29 lines
499 B
Verilog
module fulladdertb ();
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reg r1, r2, r3;
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wire w1, w2;
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fullAdder uut(
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.A(r1),
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.B(r2),
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.Cin(r3),
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.S(w1),
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.Cout(w2)
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);
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initial begin
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$dumpfile("fdmp.vcd");
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$dumpvars;
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r1 = 0; r2 = 0; r3 = 0; #10
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r1 = 0; r2 = 0; r3 = 1; #10
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r1 = 0; r2 = 1; r3 = 0; #10
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r1 = 0; r2 = 1; r3 = 1; #10
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r1 = 1; r2 = 0; r3 = 0; #10
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r1 = 1; r2 = 0; r3 = 1; #10
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r1 = 1; r2 = 1; r3 = 0; #10
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r1 = 1; r2 = 1; r3 = 1; #10
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$display(w1);
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$display(w2);
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end
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endmodule |