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formatter test

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k0rrluna 2024-12-02 02:29:38 +03:00
parent a69386c7b4
commit 1bbcfd0963
1 changed files with 3 additions and 7 deletions
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iverilog/nand2tetris/nands/andGate.v
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@ -1,16 +1,12 @@
module andGate ( module andGate (
input wire A_i, input wire A_i,
input wire B_i, input wire B_i,
output wire Y_o output wire Y_o
); );
wire nand_out; wire nand_out;
nand nand1 (nand_out, A_i, B_i); nand nand1 (nand_out, A_i, B_i);
nand nand2 (Y_o, nand_out, nand_out); nand nand2 (Y_o, nand_out, nand_out);
endmodule endmodule