formatter test

2024-12-02 02:29:38 +03:00 · 2024-12-02 02:29:38 +03:00 · 1bbcfd0963
commit 1bbcfd0963
parent a69386c7b4
1 changed files with 3 additions and 7 deletions
--- a/iverilog/nand2tetris/nands/andGate.v
+++ b/iverilog/nand2tetris/nands/andGate.v
@ -1,16 +1,12 @@
-
 module andGate (
-   input  wire A_i,
-   input  wire B_i,
-   output wire Y_o
+    input  wire A_i,
+    input  wire B_i,
+    output wire Y_o
 );

-
   wire nand_out;

-
   nand nand1 (nand_out, A_i, B_i);
-
   nand nand2 (Y_o, nand_out, nand_out);

 endmodule