diff --git a/iverilog/nand2tetris/nands/andGate.v b/iverilog/nand2tetris/nands/andGate.v
index 7ae875c..69a32ba 100644
--- a/iverilog/nand2tetris/nands/andGate.v
+++ b/iverilog/nand2tetris/nands/andGate.v
@@ -1,16 +1,12 @@
-
 module andGate (
-   input  wire A_i,
-   input  wire B_i,
-   output wire Y_o
+    input  wire A_i,
+    input  wire B_i,
+    output wire Y_o
 );
 
-
    wire nand_out;
 
-
    nand nand1 (nand_out, A_i, B_i);
-
    nand nand2 (Y_o, nand_out, nand_out);
 
 endmodule